公开(公告)号：US20200143859A1

公开(公告)日：2020-05-07

申请号：US16735543

申请日：2020-01-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hyun Yoo Lee ,  Kang-Yong Kim

IPC: G11C7/22 ,  G11C11/4076 ,  G11C7/10

Abstract: Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal are disclosed. An example apparatus includes a clock path configured to receive a clock signal and provide internal clock signals and a command path configured to receive a command and propagate the command through the command path responsive to the internal clock signals and provide an internal command having a timing that reflects a timing of the clock signal. The example apparatus further includes a data clock path configured to receive a data clock signal and provide multiphase clock signals based on the data clock signal and provide a delayed multiphase clock signal, and further includes a clock synchronization circuit configured to receive the delayed multiphase clock signal and latch a logic level of the delayed multiphase clock signal responsive to the internal command.

公开(公告)号：US10565151B2

公开(公告)日：2020-02-18

申请号：US16019254

申请日：2018-06-26

Applicant: Micron Technology, Inc.

Inventor： Hyun Yoo Lee

IPC: G06F13/40 ,  G11C29/50 ,  G11C29/02 ,  H05K1/02 ,  H04L25/02 ,  G06F13/00

Abstract: Methods, systems, and apparatuses related to memory operation with common clock signals are provided. A memory device or system that includes one or more memory devices may be operable with a common clock signal without a delay from switching on-die termination on or off. For example, a memory device may comprise first impedance adjustment circuitry configured to provide a first impedance to a received clock signal having a clock impedance and second impedance adjustment circuitry configured to provide a second impedance to the received clock signal. The first impedance and the second impedance may be configured to provide a combined impedance about equal to the clock impedance when the first impedance adjustment circuitry and the second impedance adjustment circuitry are connected to the received clock signal in parallel.

公开(公告)号：US10269397B2

公开(公告)日：2019-04-23

申请号：US15692993

申请日：2017-08-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hyun Yoo Lee

IPC: G11C8/00 ,  G11C7/22

Abstract: Apparatuses and methods for providing active an inactive clock signals are disclosed. An example apparatus includes an input clock buffer and a clock divider circuit. The input clock buffer includes a receiver circuit configured to receive first and second clock signals or first and second constant voltages. The receiver circuit is further configured to provide first and second output signals based on the complementary clock signals or the first and second constant voltages. The first and second clock signals are complementary and the second constant voltage is less than the first constant voltage. The clock divider circuit is configured to receive the first and second output signals and provide multiphase clock signals based on the first and second output signals from the input clock buffer.

公开(公告)号：US20190102109A1

公开(公告)日：2019-04-04

申请号：US15722769

申请日：2017-10-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee ,  John D. Porter

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0679 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4087

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. An example method includes receiving a data clock signal responsive to receiving a timing command, performing an access operation responsive to receiving an access command associated with the timing command, providing an access data clock signal based on the data clock signal, and providing an access data clock signal based on the data clock signal. The access command may be separated in time from the associated timing command by at least one clock cycle of a system clock signal. In some examples, the access command may precede the associated timing command or may follow the associated timing command. In some examples, the access command may immediately follow or precede the associated timing command.

公开(公告)号：US20190027199A1

公开(公告)日：2019-01-24

申请号：US16143082

申请日：2018-09-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hyun Yoo Lee ,  Kang-Yong Kim

IPC: G11C7/22 ,  G11C7/10 ,  G11C11/4076

Abstract: Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal are disclosed. An example apparatus includes a clock path configured to receive a clock signal and provide internal clock signals and a command path configured to receive a command and propagate the command through the command path responsive to the internal clock signals and provide an internal command having a timing that reflects a timing of the clock signal. The example apparatus further includes a data clock path configured to receive a data clock signal and provide multiphase clock signals based on the data clock signal and provide a delayed multiphase clock signal, and further includes a clock synchronization circuit configured to receive the delayed multiphase clock signal and latch a logic level of the delayed multiphase clock signal responsive to the internal command.

公开(公告)号：US20180247690A1

公开(公告)日：2018-08-30

申请号：US15445795

申请日：2017-02-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hyun Yoo Lee ,  Jongtae Kwak ,  Suryanarayana Tatapudi

IPC: G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G06F1/12 ,  G11C11/4093

CPC classification number: G11C7/00 ,  G06F1/12 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4093 ,  G11C11/4096 ,  G11C19/00

Abstract: In an example apparatus, a command path receives read commands and provides respective control signals for each read command. The command path is configured to provide initial control signals for an initial read command responsive to a first clock edge of a clock signal of a plurality of multiphase clock signals and to further provide respective control signals for subsequent read commands responsive to receipt of the subsequent read commands. The example apparatus further includes a read data output circuit configured to receive the control signals from the command path and further receive read data in parallel. The read data output circuit is configured to provide the read data serially responsive to the control signals.

公开(公告)号：US12176061B2

公开(公告)日：2024-12-24

申请号：US18420404

申请日：2024-01-23

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee ,  Timothy M. Hollis ,  Dong Soon Lim

IPC: G11C7/10 ,  G06F3/06 ,  G06F13/16 ,  G11C7/22 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/10

Abstract: Described apparatuses and methods enable communication between a host device and a memory device to establish relative delays between different data lines. If data signals propagate along a bus with the same timing, simultaneous switching output (SSO) and crosstalk can adversely impact channel timing budget parameters. An example system includes an interconnect having multiple data lines that couple the host device to the memory device. In example operations, the host device can transmit to the memory device a command indicative of a phase offset between two or more data lines of the multiple data lines. The memory device can implement the command by transmitting or receiving signals via the interconnect with different relative phase offsets between data lines. The host device (e.g., a memory controller) can determine appropriate offsets for a given apparatus. Lengths of the offsets can vary. Further, a system can activate the phase offsets based on frequency.

公开(公告)号：US11947840B2

公开(公告)日：2024-04-02

申请号：US17513311

申请日：2021-10-28

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee

IPC: G06F3/06 ,  G11C11/406

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G11C11/40611 ,  G11C11/40615

Abstract: Described systems, apparatuses, and methods relate to volatile memories that are refreshed to maintain data integrity, such as dynamic random-access memory (DRAM) and synchronous DRAM (SDRAM). A memory device includes multiple dies, with each die having a memory array to be refreshed. The multiple dies may be interconnected via at least one inter-die bus of the memory device. A memory controller sends a command to the memory device to enter a self-refresh mode. In response, a die of the multiple dies can enter the self-refresh mode and initiate or otherwise coordinate refresh operations of the other dies. To do so, the die may transmit at least one refresh-related command to at least one other die using the inter-die bus. Multiple different signaling schemes and timing approaches are disclosed. The described inter-die refresh control principles may be implemented in energy-efficient applications, such as in low-power double data rate (LPDDR) SDRAM.

公开(公告)号：US11922061B2

公开(公告)日：2024-03-05

申请号：US17458068

申请日：2021-08-26

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee

IPC: G06F3/06 ,  G11C11/406

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G11C11/40615

Abstract: Systems, apparatuses, and methods related to a memory device and an associated host device are described. The memory device and the host device can include control logic that allow the memory device and host device to share refresh-timing information, which may allow either the memory device or the host, or both, to manage operations during time that is dedicated to, but unused for, refresh or self-refresh operations. Refresh-timing information shared from the host device may indicate elapsed time since the host device issued a refresh command to the memory device and/or how much time remains before the host device is scheduled to issue another refresh command. Refresh-timing information shared from the memory device may indicate elapsed time since the memory device performed a self-refresh operation and/or how much time remains before the memory device is scheduled to initiate or undergo another self-refresh operation.

公开(公告)号：US20240071461A1

公开(公告)日：2024-02-29

申请号：US17823407

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： John Christopher Sancon ,  Kang-Yong Kim ,  Yang Lu ,  Hyun Yoo Lee

IPC: G11C11/406 ,  G11C11/4096

CPC classification number: G11C11/40622 ,  G11C11/40615 ,  G11C11/4096

Abstract: Described apparatuses and methods relate to adaptive memory registers for a memory system that may support a nondeterministic protocol. To help manage power-delivery networks in a memory system, a device includes logic that can write values to memory registers associated with memory blocks of a memory array. The values indicate whether an associated memory block has been refreshed within a refresh interval. Other logic can read the registers to determine whether a block has been refreshed. The device also includes logic that can access data indicating a row address that was most recently, or is next to be, refreshed and write values representing the address to another register. The register can be read by other logic to determine whether a wordline potentially affected by an activation-based disturb event is near to being refreshed. These techniques can reduce the number of refresh operations performed, saving power and reducing costs.