公开(公告)号：US20220293144A1

公开(公告)日：2022-09-15

申请号：US17805267

申请日：2022-06-03

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim

IPC: G11C7/10 ,  G11C8/10 ,  G11C8/18

Abstract: Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space.

公开(公告)号：US11360695B2

公开(公告)日：2022-06-14

申请号：US17022551

申请日：2020-09-16

Applicant: Micron Technology, Inc.

Inventor： Hyun Yoo Lee ,  Kang-Yong Kim

IPC: G06F3/00 ,  G06F3/06 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4096

Abstract: Methods, apparatuses, and systems related to combining and utilizing multiple memory circuits having complementary characteristics are described. An apparatus may include a first memory circuit having a first characteristic and a second memory circuit having a second characteristic. Contact pads of the first and second memory circuits may be connected in parallel and to a common interface configured to communicate data between the apparatus and an external device.

公开(公告)号：US20220068365A1

公开(公告)日：2022-03-03

申请号：US17459446

申请日：2021-08-27

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee

IPC: G11C11/406

Abstract: Systems, apparatuses, and methods related to a memory device, such as a low-power dynamic random-access memory (DRAM) and an associated host device are described. The memory device and the host device can include control logic that enables the host device to transmit a burst value to the memory device, which may enable the memory device, the host, or both, to manage refresh operations during a normal operation mode or a self-refresh mode. The burst value can be transmitted to the memory device in association with a command (e.g., a command directing the memory device to enter the self-refresh mode). The burst value can specify a number of self-refresh operations to be initiated at the memory device in response to receiving the command. When the specified number of self-refresh operations are completed, regular self-refresh operations may begin, with an internal self-refresh timer counting an interval to the next self-refresh operation.

公开(公告)号：US20220066675A1

公开(公告)日：2022-03-03

申请号：US17018570

申请日：2020-09-11

Applicant: Micron Technology, Inc.

Inventor： Sourabh Dhir ,  Kang-Yong Kim

IPC: G06F3/06

Abstract: Methods, systems, and devices for improved inter-memory movement in a multi-memory system are described. A memory device may receive from a host device a command to move data from a first memory controlled by a first controller to a second memory controller by a second controller. The memory device may use the first and second controllers to facilitate the movement of the data from the first memory to the second memory via a path external to the host device. The memory device may indicate to the host device when to suspend activity to the first memory or the second memory and when to resume activity to the first memory or second memory.

公开(公告)号：US20210398601A1

公开(公告)日：2021-12-23

申请号：US17349612

申请日：2021-06-16

Applicant: Micron Technology, Inc.

Inventor： Taeksang Song ,  Hyunyoo Lee ,  Saira Samar Malik ,  Kang-Yong Kim

IPC: G11C29/10 ,  G11C29/36 ,  G11C29/12 ,  G11C29/14 ,  G11C29/18

Abstract: Methods, systems, and devices for direct testing of in-package memory are described. A memory subsystem package may include non-volatile memory, volatile memory that may be configured as a cache, and a controller. The memory subsystem may support direct access to the non-volatile memory for testing the non-volatile memory in the package using a host interface of the memory subsystem rather than using dedicated contacts on the package. To ensure deterministic behavior during testing operations, the memory subsystem may, when operating with a test mode enabled, forward commands received from a host device (such as automated test equipment) to a memory interface of the non-volatile memory and bypass the cache-related circuitry. The memory subsystem may include a separate conductive path that bypasses the cache for forwarding commands and addresses to the memory interface during testing.

公开(公告)号：US11145341B2

公开(公告)日：2021-10-12

申请号：US17202553

申请日：2021-03-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim

IPC: G11C7/22 ,  G11C7/10 ,  H03K5/156 ,  G11C11/4076

Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.

公开(公告)号：US20210201971A1

公开(公告)日：2021-07-01

申请号：US17202553

申请日：2021-03-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim

IPC: G11C7/22 ,  G11C7/10 ,  H03K5/156 ,  G11C11/4076

Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.

公开(公告)号：US10902897B2

公开(公告)日：2021-01-26

申请号：US16995568

申请日：2020-08-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim

IPC: G11C8/00 ,  G11C7/22 ,  G11C7/10 ,  G11C11/4076 ,  H03K5/156

Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.

公开(公告)号：US20200233592A1

公开(公告)日：2020-07-23

申请号：US16838873

申请日：2020-04-02

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim

IPC: G06F3/06 ,  G06F12/02

Abstract: Methods, systems, and devices for a low-speed memory operation are described. A controller associated with a memory device may, for example, identify a clock mode for a system clock and determine that a speed of the system clock is below a threshold. The controller may generate (or cause to be generated) an internal data clock signal having a shorter period than an external data clock signal (which may have a speed based on the system clock speed). Also, the controller may use, instead of the external data clock signal, the internal data clock signal to generate data from the memory device, which may provide reduced latency. Further, the controller may deactivate (or cause to be deactivated) an external data clock that generates the external data clock signal. Such techniques may provide improved data bandwidth, improved command bandwidth, and/or reduced power consumption.

公开(公告)号：US20200176038A1

公开(公告)日：2020-06-04

申请号：US16781949

申请日：2020-02-04

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim

IPC: G11C7/22 ,  G06F13/16 ,  G06F1/12

Abstract: Methods, systems, and devices for system-level timing budget improvements are described. Each memory die in a memory device may determine an offset between its system clock signal and its data clock signal. The offsets of each memory die in the memory device may be different; e.g., having different magnitudes and/or polarities. A memory die in the memory device may adjust its own data clock signal by a delay that is based on the offsets of two or more memory die in the device. The memory die may adjust its data clock signal by setting a fuse in a delay adjuster on the memory die. Adjusting the data clock signal may match an offset of a first memory die with an offset of a second memory die.