公开(公告)号：US20210064460A1

公开(公告)日：2021-03-04

申请号：US16554913

申请日：2019-08-29

Applicant: Micron Technology, Inc.

Inventor： Aaron Jannusch ,  Brett K. Dodds ,  Debra M. Bell ,  Joshua M. Alzheimer ,  Scott E. Smith

IPC: G06F11/10

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may access a group of memory cells (e.g., portion of an array configurable to store ECC parity bits) otherwise reserved for ECC functionality of a memory device. The memory device may include a register to indicate whether its ECC functionality is enabled or disabled. When the register indicates the ECC functionality is disabled, the memory device may increase a storage capacity available to the host device by making the group of memory cells available for user-accessible data. Additionally or alternatively, the memory device may store metadata associated with various operational aspects of the memory device in the group of memory cells. Moreover, the memory device may modify a burst length to accommodate additional information to be stored in or read from the group of memory cells.

公开(公告)号：US10854270B2

公开(公告)日：2020-12-01

申请号：US16522240

申请日：2019-07-25

Applicant: Micron Technology, Inc.

Inventor： Scott E. Smith ,  Michael A. Shore

IPC: G11C11/406 ,  G11C11/408

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which redundancy match is disabled to permit activating more word lines in parallel during refresh operations to increase a refresh rate of memory cells in a memory array. In one embodiment, a memory device is provided, comprising a memory array including a plurality of word lines arranged in a plurality of memory banks. The memory device further comprises circuitry configured to (i) store a value indicating one or more addresses corresponding to word lines in the plurality of word lines, (ii) disable redundancy match, (iii) activate one or more first word lines in the memory array corresponding to the one or more addresses indicated by the value to refresh first data stored in the memory array, and (iv) update the value based at least in part on activating the one or more first word lines.

公开(公告)号：US20200303349A1

公开(公告)日：2020-09-24

申请号：US16894568

申请日：2020-06-05

Applicant: Micron Technology, Inc.

Inventor： Christian N. Mohr ,  Scott E. Smith

IPC: H01L25/065 ,  G01R27/14 ,  H01L23/538

Abstract: Semiconductor devices having through-stack interconnects for facilitating connectivity testing, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a stack of semiconductor dies and a plurality of through-stack interconnects extending through the stack to electrically couple the semiconductor dies. The interconnects include functional interconnects and at least one test interconnect. The test interconnect is positioned in a portion of the stack more prone to connectivity defects than the functional interconnects. Accordingly, testing the connectivity of the test interconnect can provide an indication of the connectivity of the functional interconnects.

公开(公告)号：US20200227118A1

公开(公告)日：2020-07-16

申请号：US16249714

申请日：2019-01-16

Applicant: Micron Technology, Inc.

Inventor： Gary L. Howe ,  Scott E. Smith

IPC: G11C16/08 ,  G11C8/10 ,  G11C7/06

Abstract: Apparatuses and methods for decoding addresses for memory are disclosed. An example apparatus includes a memory cell array and a row decoder. The memory cell array includes a bank of memory including a plurality of groups of memory. Each of the groups of memory includes sections of memory, and each of the sections of memory including memory cells arranged in rows and columns of memory. The row decoder decodes addresses to access a first group of memory to include rows of prime memory from a first block of memory and to include rows of prime memory from a second block of memory. The row decoder decodes the addresses to access a second group of memory to include rows of prime memory from the second block of memory and to include rows of redundant memory. The rows of redundant memory are shared with the first and second blocks of memory.

公开(公告)号：US10699774B2

公开(公告)日：2020-06-30

申请号：US16189434

申请日：2018-11-13

Applicant: Micron Technology, Inc.

Inventor： Michael V. Ho ,  Scott E. Smith

IPC: G11C11/24 ,  G11C11/4096 ,  G11C11/408 ,  G11C11/22 ,  G11C11/4094 ,  G11C11/4091 ,  G11C7/10 ,  G11C7/02 ,  G11C11/4097 ,  G11C7/18

Abstract: Methods, systems, and devices for mitigating line-to-line capacitive coupling in a memory die are described. A device may include multiple drivers configured to both drive latched data and conduct read and write operations. For example, a memory device may contain two or more memory arrays independently coupled to two drivers via two data lines. One data line may be driven strongly to shield a corresponding memory array from effects associated with data line capacitive coupling. An opposing data line may be driven with data pertaining to an access operation of the memory array to which it is coupled. The opposing data line may be driven concurrently or within a small time difference of the other data line.

公开(公告)号：US10373698B1

公开(公告)日：2019-08-06

申请号：US15967022

申请日：2018-04-30

Applicant: Micron Technology, Inc.

Inventor： John E. Riley ,  Girish N. Cherussery ,  Scott E. Smith ,  Yu-Feng Chen

IPC: G11C7/00 ,  G11C17/16 ,  G11C7/10 ,  H01L23/525 ,  G11C11/34 ,  G11C29/00

Abstract: An electronic device including: a fuse array including fuse cells organized along a first direction and a second direction, wherein each fuse cell includes: a fuse element configured to store information, and a selection circuit configured to provide access to the fuse element according to a position of the fuse cell element along the first direction and the second direction; and a fuse read circuit connected to the fuse array, the fuse read circuit configured to generate a fuse read output based on reading from one or more of the fuse cells simultaneously and in parallel.

公开(公告)号：US10332609B1

公开(公告)日：2019-06-25

申请号：US15851129

申请日：2017-12-21

Applicant: Micron Technology, Inc.

Inventor： John E. Riley ,  Yu-Feng Chen ,  Scott E. Smith

IPC: G11C17/16 ,  G11C17/18 ,  G11C7/22 ,  G11C29/00 ,  G11C7/10 ,  G11C29/04

CPC classification number: G11C17/16 ,  G11C7/1006 ,  G11C7/22 ,  G11C17/18 ,  G11C29/04 ,  G11C29/812

Abstract: A memory device includes a memory bank accessible via a plurality of memory addresses. The memory device further includes a fuse array comprising a plurality of fuses. The memory device additionally includes a first plurality of local fuse latches disposed outside of the fuse array and configured to provide redundancy for the plurality of memory addresses. The memory device also includes a fuse array broadcasting system comprising an N-bit bus system, wherein the N-bit bus system is communicatively coupled to the fuse array and to the first plurality of local fuse latches, and wherein the fuse array broadcasting system is configured to communicate fuse data from the fuse array to the first plurality of local fuse latches via the N-bit bus system.