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1.发明申请公开(公告)号：US20200303349A1
公开(公告)日：2020-09-24
申请号：US16894568
申请日：2020-06-05
发明人： Christian N. Mohr , Scott E. Smith
IPC分类号： H01L25/065 , G01R27/14 , H01L23/538
摘要： Semiconductor devices having through-stack interconnects for facilitating connectivity testing, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a stack of semiconductor dies and a plurality of through-stack interconnects extending through the stack to electrically couple the semiconductor dies. The interconnects include functional interconnects and at least one test interconnect. The test interconnect is positioned in a portion of the stack more prone to connectivity defects than the functional interconnects. Accordingly, testing the connectivity of the test interconnect can provide an indication of the connectivity of the functional interconnects.
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2.发明授权公开(公告)号：US11842985B2
公开(公告)日：2023-12-12
申请号：US17965561
申请日：2022-10-13
发明人： Christian N. Mohr , Scott E. Smith
IPC分类号： G01R27/14 , H01L25/065 , H01L23/538
CPC分类号： H01L25/0657 , G01R27/14 , H01L23/5385
摘要： Semiconductor devices having through-stack interconnects for facilitating connectivity testing, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a stack of semiconductor dies and a plurality of through-stack interconnects extending through the stack to electrically couple the semiconductor dies. The interconnects include functional interconnects and at least one test interconnect. The test interconnect is positioned in a portion of the stack more prone to connectivity defects than the functional interconnects. Accordingly, testing the connectivity of the test interconnect can provide an indication of the connectivity of the functional interconnects.
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3.发明授权公开(公告)号：US11495577B2
公开(公告)日：2022-11-08
申请号：US16894568
申请日：2020-06-05
发明人： Christian N. Mohr , Scott E. Smith
IPC分类号： H01L25/065 , G01R27/14 , H01L23/538
摘要： Semiconductor devices having through-stack interconnects for facilitating connectivity testing, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a stack of semiconductor dies and a plurality of through-stack interconnects extending through the stack to electrically couple the semiconductor dies. The interconnects include functional interconnects and at least one test interconnect. The test interconnect is positioned in a portion of the stack more prone to connectivity defects than the functional interconnects. Accordingly, testing the connectivity of the test interconnect can provide an indication of the connectivity of the functional interconnects.
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公开(公告)号：US20200098398A1
公开(公告)日：2020-03-26
申请号：US16143105
申请日：2018-09-26
发明人： Christian N. Mohr , John E. Riley
摘要： Memory devices may have internal circuitry that employs voltages higher and/or lower than voltages provided by an external power source. Charge pumps are DC/DC converters that may be used to generate the higher voltages internally. The number of available charge pumps in a memory device may be conservatively dimensioned to be high, in some systems to protect yields. Some of the available charge pumps may be disabled during manufacturing or testing to reduce the number of active charge pumps. The testing process may employ dedicated logic in the memory device and the disabling may employ fuse circuitry.
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公开(公告)号：US11810641B2
公开(公告)日：2023-11-07
申请号：US16926505
申请日：2020-07-10
IPC分类号： G11C7/10 , G11C11/4093 , H03F3/45
CPC分类号： G11C7/1084 , G11C7/1096 , G11C11/4093 , H03F3/45475
摘要： Apparatuses and methods for trimming input buffers based on identified mismatches. An example apparatus includes an input buffer having a first input stage circuit configured to receive a first signal, a second input stage circuit configured to receive a second signal, and an output stage coupled to the first and second input stage circuits and configured to provide an output signal. The first input stage circuit includes serially-coupled transistor pairs that are each coupled between the output stage and a bias voltage. Each of the plurality of serially-coupled transistors pairs are selectively enabled in response to a respective enable signal. The apparatus further including a trim circuit coupled to the first input stage circuit and comprising a plurality of programmable components. The trim circuit is configured to be programmed to provide the respective enable signals based on a detected transition voltage offset relative to a target transition voltage.
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公开(公告)号：US20210210122A1
公开(公告)日：2021-07-08
申请号：US17205705
申请日：2021-03-18
发明人： Christian N. Mohr , John E. Riley
摘要： Memory devices may have internal circuitry that employs voltages higher and/or lower than voltages provided by an external power source. Charge pumps are DC/DC converters that may be used to generate the higher voltages internally. The number of available charge pumps in a memory device may be conservatively dimensioned to be high, in some systems to protect yields. Some of the available charge pumps may be disabled during manufacturing or testing to reduce the number of active charge pumps. The testing process may employ dedicated logic in the memory device and the disabling may employ fuse circuitry.
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公开(公告)号：US20200342922A1
公开(公告)日：2020-10-29
申请号：US16926505
申请日：2020-07-10
IPC分类号： G11C7/10
摘要： Apparatuses and methods for trimming input buffers based on identified mismatches. An example apparatus includes an input buffer having a first input stage circuit configured to receive a first signal, a second input stage circuit configured to receive a second signal, and an output stage coupled to the first and second input stage circuits and configured to provide an output signal. The first input stage circuit includes serially-coupled transistor pairs that are each coupled between the output stage and a bias voltage. Each of the plurality of serially-coupled transistors pairs are selectively enabled in response to a respective enable signal. The apparatus further including a trim circuit coupled to the first input stage circuit and comprising a plurality of programmable components. The trim circuit is configured to be programmed to provide the respective enable signals based on a detected transition voltage offset relative to a target transition voltage.
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公开(公告)号：US20200243155A1
公开(公告)日：2020-07-30
申请号：US16852239
申请日：2020-04-17
发明人： Christian N. Mohr , Gregg D. Wolff , Christopher G. Wieduwilt , C. Omar Benitez , Dennis G. Montierth
摘要： An apparatus may include a memory array, a test circuit coupled to the memory array, a counter circuit coupled to the test circuit and an input/output (I/O) circuit coupled to the counter circuit. During a test operation, the test circuit may receive blocks of data from the memory array and compare the data to detect errors in the blocks of data. The counter circuit may increment a count value in response to detection of an error by the test circuit, and the I/O circuit may provide the count value to an output. The test circuit may also provide test comparison data based on the received blocks of data, and the I/O circuit may provide one of the count value and the test comparison data to the output.
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9.发明申请公开(公告)号：US20200006291A1
公开(公告)日：2020-01-02
申请号：US16020140
申请日：2018-06-27
发明人： Christian N. Mohr , Scott E. Smith
IPC分类号： H01L25/065 , H01L23/538 , G01R27/14
摘要： Semiconductor devices having through-stack interconnects for facilitating connectivity testing, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a stack of semiconductor dies and a plurality of through-stack interconnects extending through the stack to electrically couple the semiconductor dies. The interconnects include functional interconnects and at least one test interconnect. The test interconnect is positioned in a portion of the stack more prone to connectivity defects than the functional interconnects. Accordingly, testing the connectivity of the test interconnect can provide an indication of the connectivity of the functional interconnects.
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公开(公告)号：US11984189B2
公开(公告)日：2024-05-14
申请号：US17205705
申请日：2021-03-18
发明人： Christian N. Mohr , John E. Riley
摘要： Memory devices may have internal circuitry that employs voltages higher and/or lower than voltages provided by an external power source. Charge pumps are DC/DC converters that may be used to generate the higher voltages internally. The number of available charge pumps in a memory device may be conservatively dimensioned to be high, in some systems to protect yields. Some of the available charge pumps may be disabled during manufacturing or testing to reduce the number of active charge pumps. The testing process may employ dedicated logic in the memory device and the disabling may employ fuse circuitry.
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