公开(公告)号：US20190074841A1

公开(公告)日：2019-03-07

申请号：US15697773

申请日：2017-09-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yasuo Satoh

IPC: H03L7/099 ,  H03L7/089 ,  H03L7/081 ,  H03L7/10

CPC classification number: H03L7/0992 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4093 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/089 ,  H03L7/10

Abstract: Apparatuses and methods are disclosed for detecting a loop count in a delay-locked loop that uses a divide clock in a measure initialization process. An example apparatus includes a divider configured to receive a signal and produce a first divided signal and a second divided signal that is complementary to the first divided signal, a first circuit configured to count the first divided signal during a first enabled period and produce a first count value, a second circuit configured to count the second divided signal during a second enabled period and produce a second count value, and an adder configured to produce a third count value responsive to the first and second count values.

公开(公告)号：US09124253B2

公开(公告)日：2015-09-01

申请号：US14058092

申请日：2013-10-18

Applicant: Micron Technology, Inc.

Inventor： Tyler J. Gomm ,  Yasuo Satoh

IPC: H03L5/00 ,  H03K3/017 ,  H03L7/06 ,  H03K5/156

CPC classification number: H03K3/017 ,  H03K5/1565 ,  H03L7/06

Abstract: Methods and apparatuses are disclosed for preserving duty cycle at voltage domain boundaries. One example apparatus includes a complement generation circuit configured to generate a complementary signal responsive to an input signal. The complement generation circuit is configured to operate in a first voltage domain. The apparatus also includes a compensation circuit configured to generate a compensated signal by compensating the input signal for a delay corresponding to the complement generation circuit. The compensation circuit is configured to operate in a second voltage domain. The apparatus also includes a phase mixing circuit configured to combine the complementary signal and the compensated signal to generate an output signal.

Abstract translation: 公开了用于在电压域边界处保持占空比的方法和装置。 一个示例性装置包括补码生成电路，其被配置为响应于输入信号产生互补信号。 补码生成电路被配置为在第一电压域中操作。 该装置还包括补偿电路，其被配置为通过对与补码生成电路相对应的延迟补偿输入信号来产生补偿信号。 补偿电路被配置为在第二电压域中操作。 该装置还包括相位混合电路，该相位混合电路被配置为组合互补信号和经补偿的信号以产生输出信号。