公开(公告)号：US20220230671A1

公开(公告)日：2022-07-21

申请号：US17700346

申请日：2022-03-21

Applicant: Micron Technology, Inc.

Inventor： Yasuo Satoh

IPC: G11C11/4076 ,  H03L7/081 ,  H03K5/14 ,  H03K5/131

Abstract: Apparatuses and methods for adjusting a phase mixer circuit are disclosed. An example method includes providing data values stored by a plurality of first registers and a plurality of second registers. The method includes: during a first mode of operation, receiving the data values by groups of first registers of the plurality of the first registers and holding the data values by the plurality of second registers; during a second mode of operation, inverting a data value by one first register of the plurality of first registers at a time and holding the data values by the plurality of second registers; and during a third mode of operation, either inverting the data value by one first register of the plurality of first registers while holding the data values by the plurality of second registers or inverting a data value by one second register of the plurality of second registers while holding the data values by the plurality of first registers.

公开(公告)号：US20210149423A1

公开(公告)日：2021-05-20

申请号：US16987262

申请日：2020-08-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yuan He ,  Yasuo Satoh

IPC: G05F1/46 ,  G11C5/06 ,  G11C7/10 ,  H03K19/00

Abstract: In an example semiconductor device, the voltage/temperature conditions of the semiconductor device and associated calibration codes of multiple instances of ZQ calibrations are pre-stored in a register array. When a pre-stored voltage/temperature condition occurs again, ZQ calibration is not performed. Instead, the associated pre-stored calibration code is retrieved from the register array and provided to the IO circuit. When a voltage/temperature condition of the semiconductor device does not match any pre-stored voltage/temperature condition in the register array, a ZQ calibration is performed. When the ZQ calibration is performed, a register in the register array is selected according to an update policy and updated by the calibration code newly provided by the ZQ calibration along with the voltage/temperature condition at the time when the ZQ calibration is performed.

公开(公告)号：US10770130B2

公开(公告)日：2020-09-08

申请号：US16557933

申请日：2019-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yasuo Satoh ,  Tyler J. Gomm

IPC: G11C11/4076 ,  H03K3/017 ,  H03K23/00 ,  H03M7/16 ,  G11C29/02 ,  H03K5/156 ,  G11C7/22 ,  H03K19/21

Abstract: Apparatuses and methods for maintaining a duty cycle error counter. An example apparatus may a duty cycle detect circuit configured to receive a clock signal and to detect a duty cycle error of the clock signal. The duty cycle detect error includes a counter configured to store a count value indicating the duty cycle error using Gray code. The counter is adjusted in response to detection of non-zero duty cycle error, and the counter is configured to convert the count value from Gray code to binary code as a binary count value. The duty cycle detect circuit is further configured to provide a duty cycle error signal based on the binary count value. The example apparatus further comprising a duty cycle correction circuit configured to adjust a duty cycle of the clock signal based on the duty cycle error signal.

公开(公告)号：US10747245B1

公开(公告)日：2020-08-18

申请号：US16688870

申请日：2019-11-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yuan He ,  Yasuo Satoh

IPC: G05F1/46 ,  G11C7/10 ,  G11C5/06 ,  H03K19/00

Abstract: In an example semiconductor device, the voltage/temperature conditions of the semiconductor device and associated calibration codes of multiple instances of ZQ calibrations are pre-stored in a register array. When a pre-stored voltage/temperature condition occurs again, ZQ calibration is not performed. Instead, the associated pre-stored calibration code is retrieved from the register array and provided to the IO circuit. When a voltage/temperature condition of the semiconductor device does not match any pre-stored voltage/temperature condition in the register array, a ZQ calibration is performed. When the ZQ calibration is performed, a register in the register array is selected according to an update policy and updated by the calibration code newly provided by the ZQ calibration along with the voltage/temperature condition at the time when the ZQ calibration is performed.

公开(公告)号：US10700689B2

公开(公告)日：2020-06-30

申请号：US16746352

申请日：2020-01-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yasuo Satoh

IPC: H03L7/099 ,  H03L7/081 ,  G11C7/10 ,  H03L7/10 ,  G11C11/4093 ,  H03L7/089 ,  G11C7/22

Abstract: Apparatuses and methods are disclosed for detecting a loop count in a delay-locked loop that uses a divide clock in a measure initialization process. An example apparatus includes a divider configured to receive a signal and produce a first divided signal and a second divided signal that is complementary to the first divided signal, a first circuit configured to count the first divided signal during a first enabled period and produce a first count value, a second circuit configured to count the second divided signal during a second enabled period and produce a second count value, and an adder configured to produce a third count value responsive to the first and second count values.

公开(公告)号：US20190288674A1

公开(公告)日：2019-09-19

申请号：US15923860

申请日：2018-03-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yasuo Satoh

IPC: H03K5/135 ,  G11C27/04

Abstract: Apparatuses and methods for adjusting a phase mixer circuit are disclosed. An example apparatus includes a shift register that includes a plurality of registers coupled in series to one another. The plurality of registers are grouped into a first group of registers and a second group of registers. The first group of registers includes first and second registers. The second group of registers includes a third register. The first and second registers of the first group of registers are configured to receive in common an output of the third register of the second group of registers so that both the first and second registers store the output of the third register responsive to a shift clock.

公开(公告)号：US20190199364A1

公开(公告)日：2019-06-27

申请号：US16150492

申请日：2018-10-03

Applicant: Micron Technology, Inc.

Inventor： Yasuo Satoh

IPC: H03L7/14 ,  H03L7/087 ,  H03L7/18 ,  H04L7/04 ,  H04L5/26

CPC classification number: H03L7/143 ,  H03K5/1565 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/18 ,  H04L5/26 ,  H04L7/04

Abstract: Apparatuses and methods for providing frequency divided clocks are described. An example apparatus includes a first circuit configured to provide a first intermediate clock responsive, at least in part, to a first input clock, the first intermediate clock being lower in frequency than the first input clock and further includes a second circuit configured to provide a second intermediate clock and a third intermediate clock responsive, at least in part, to a second input clock, the second intermediate clock being complementary to the third intermediate clock and lower in frequency than the second input clock. The apparatus further includes a third circuit configured to select and provide as an output clock one of the second and third intermediate clocks responsive, at least in part, to the first and second intermediate clocks.

公开(公告)号：US12244316B2

公开(公告)日：2025-03-04

申请号：US18624648

申请日：2024-04-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yasuo Satoh

IPC: H03K5/156 ,  G11C11/4076

Abstract: An apparatus according to some embodiments comprises: a first clock path including a first duty-cycle adjuster that adjusts a duty cycle of a first input clock signal, a second clock path including a second duty-cycle adjuster that adjusts a duty cycle of a second input clock signal having a different phase from the first input clock signal; and a control circuit configured to detect longest one or shortest one of first, second, third, and fourth time periods to generate a control signal. The first, second, third and fourth time periods are defined by phase differences between rising edges and falling edges of the first and second input clock signals.

公开(公告)号：US11705896B2

公开(公告)日：2023-07-18

申请号：US17540846

申请日：2021-12-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yasuo Satoh

IPC: H03K5/135 ,  H03L7/081 ,  G11C7/22

CPC classification number: H03K5/135 ,  G11C7/222 ,  H03L7/0814

Abstract: Apparatuses and methods of DLL measurement initialization are disclosed. An example apparatus includes: a clock enable circuit that provides a first clock signal having a half frequency of an input clock signal and second clock signals having a quarter frequency of the input clock signal; a coarse delay that provides the first clock signal with a coarse delay; a fine delay that provides the first clock signal with the coarse delay and a fine delay as an output clock signal; a model delay having a feedback delay equivalent to a sum of delays of an input stage and an output stage, and provides a feedback signal that is the output clock signal with the feedback delay; and a measurement initialization circuit that performs measurement initialization. The measurement initialization circuit includes synchronizers that receive the feedback signal and the second clock signals, and provide a stop signal to the coarse delay.

公开(公告)号：US11705888B2

公开(公告)日：2023-07-18

申请号：US17086792

申请日：2020-11-02

Applicant: Micron Technology, Inc.

Inventor： Yasuo Satoh ,  Hiroki Takahashi ,  Shuichi Tsukada ,  Yuan He

IPC: H03K19/00 ,  H03H11/54 ,  H03H11/28

CPC classification number: H03H11/54 ,  H03H11/28 ,  H03K19/0005 ,  G11C2207/2254

Abstract: A memory device includes a terminal calibration circuit having at least one of a pull-down circuit or a pull-up circuit used in calibrating an impedance of a data bus termination. The memory device also includes a reference calibration circuit configured to generate a calibration current. The terminal calibration circuit can be configured to program an impedance of the least one of a pull-down circuit or a pull-up circuit based on the calibration current.