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100 条记录 (耗时 0.026 秒)

    INTEGRATING NON-PERIPHERAL COMPONENT INTERCONNECT (PCI) RESOURCES INTO A PERSONAL COMPUTER SYSTEM
    62.
    发明申请
    INTEGRATING NON-PERIPHERAL COMPONENT INTERCONNECT (PCI) RESOURCES INTO A PERSONAL COMPUTER SYSTEM 有权
    将非外围组件互连（PCI）资源集成到个人计算机系统

    公开(公告)号：US20100287325A1

    公开(公告)日：2010-11-11

    申请号：US12841889

    申请日：2010-07-22

    申请人： Arvind Mandhani ,  Woojong Han ,  Ken Shoemaker ,  Madhun Athreya ,  Mahesh Wagh ,  Shreekant S. Thakkar

    发明人： Arvind Mandhani ,  Woojong Han ,  Ken Shoemaker ,  Madhun Athreya ,  Mahesh Wagh ,  Shreekant S. Thakkar

    IPC分类号： G06F13/42

    CPC分类号： G06F13/4022 ,  G06F13/4027 ,  G06F13/404 ,  G06F13/4045 ,  G06F13/42

    摘要： In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，本发明包括具有根据个人计算机（PC）协议和第二协议进行通信的适配器的装置。 耦合到适配器的第一接口是对从适配器的上游接收的事务执行地址转换和排序。 第一个接口依次耦合到异构资源，每个资源包括知识产权（IP）核心和垫片，其中垫片将为IP核实现PC协议的头部，以使其能够并入设备中而无需 修改。 描述和要求保护其他实施例。

    Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC)
    63.
    发明申请
    Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC) 有权
    为芯片上的系统（SoC）提供外设组件互连（PCI）兼容的事务级协议，

    公开(公告)号：US20090300245A1

    公开(公告)日：2009-12-03

    申请号：US12156320

    申请日：2008-05-30

    申请人： Ken Shoemaker ,  Mahesh Wagh ,  Woojong Han ,  Madhu Athreya ,  Arvind Mandhani ,  Shreekant S. Thakkar

    发明人： Ken Shoemaker ,  Mahesh Wagh ,  Woojong Han ,  Madhu Athreya ,  Arvind Mandhani ,  Shreekant S. Thakkar

    IPC分类号： G06F13/42

    CPC分类号： G06F13/404 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4027 ,  G06F13/4045

    摘要： In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，本发明包括具有根据个人计算机（PC）协议和第二协议进行通信的适配器的装置。 耦合到适配器的第一接口是对从适配器的上游接收的事务执行地址转换和排序。 第一接口依次通过一个或多个物理单元耦合到异构资源，每个资源包括知识产权（IP）核心和垫片，其中垫片将实现用于IP核的PC协议的报头以使能 无需修改即可并入设备。 描述和要求保护其他实施例。

    Leveraging an enumeration and/or configuration mechanism of one interconnect protocol for a different interconnect protocol
    64.
    发明授权
    Leveraging an enumeration and/or configuration mechanism of one interconnect protocol for a different interconnect protocol 有权
    利用不同互连协议的一个互连协议的枚举和/或配置机制

    公开(公告)号：US09405718B2

    公开(公告)日：2016-08-02

    申请号：US13976548

    申请日：2013-02-28

    申请人： Sridharan Ranganathan ,  Mahesh Wagh

    发明人： Sridharan Ranganathan ,  Mahesh Wagh

    IPC分类号： G06F13/42 ,  G06F13/38 ,  G06F3/06

    CPC分类号： G06F13/42 ,  G06F3/0661 ,  G06F13/387 ,  G06F13/4027 ,  Y02D10/14 ,  Y02D10/151

    摘要： An interconnect architecture device of an aspect includes a processor to generate a transaction that is of a different interconnect protocol than LLI. The interconnect architecture device also includes conversion logic coupled with the processor. The conversion logic is to convert the transaction, which is of the different interconnect protocol than LLI, to an LLI packet. The interconnect architecture device also includes an LLI controller coupled with the conversion logic. The LLI controller is to couple the interconnect architecture device with an LLI link. The LLI controller is to transmit the LLI packet on the LLI link.

    摘要翻译： 一方面的互连架构设备包括处理器，用于生成与LLI不同的互连协议的事务。 互连架构设备还包括与处理器耦合的转换逻辑。 转换逻辑是将与LLI不同的互连协议的事务转换为LLI数据包。 互连架构设备还包括与转换逻辑耦合的LLI控制器。 LLI控制器将互连架构设备与LLI链路耦合。 LLI控制器将在LLI链路上发送LLI报文。

    METHOD, APPARATUS AND SYSTEM FOR MEASURING LATENCY IN A PHYSICAL UNIT OF A CIRCUIT
    65.
    发明申请
    METHOD, APPARATUS AND SYSTEM FOR MEASURING LATENCY IN A PHYSICAL UNIT OF A CIRCUIT 有权
    用于测量电路的物理单元中的延迟的方法，装置和系统

    公开(公告)号：US20150117504A1

    公开(公告)日：2015-04-30

    申请号：US14126926

    申请日：2013-10-30

    申请人： David J. Harriman ,  Mahesh Wagh ,  Abdul R. Ismail ,  Daniel S. Froelich

    发明人： David J. Harriman ,  Mahesh Wagh ,  Abdul R. Ismail ,  Daniel S. Froelich

    IPC分类号： H04B17/00

    CPC分类号： G06F13/4282 ,  G06F1/14 ,  G06F13/00 ,  G06F13/385 ,  H04L43/0858 ,  H04L43/106

    摘要： In an embodiment, an apparatus includes a counter to count between a start value and an end value according to a local clock signal, a first register to store an output of the counter, a mirror elastic buffer to store samples of the counter output received from the first register, where the mirror elastic buffer is to mirror an elastic buffer of a receiver circuit, and a resolution logic to receive a counter output sample from the mirror elastic buffer and a current counter value output from the counter, and to determine a transit latency for a data element to traverse the receiver circuit based at least in part on the counter output sample and the current counter value. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，装置包括根据本地时钟信号在起始值和结束值之间进行计数的计数器，用于存储计数器的输出的第一寄存器，用于存储接收到的计数器输出的样本的镜像弹性缓冲器 第一寄存器，其中反射镜弹性缓冲器用于映射接收器电路的弹性缓冲器，以及分辨率逻辑，用于从反射镜弹性缓冲器接收计数器输出样本，以及从计数器输出的当前计数器值，并确定传送 数据元素至少部分地基于计数器输出采样和当前计数器值来遍历接收器电路的等待时间。 描述和要求保护其他实施例。

    DEVICE, SYSTEM AND METHOD FOR COMMUNICATION WITH HETEROGENOUS PHYSICAL LAYERS
    66.
    发明申请
    DEVICE, SYSTEM AND METHOD FOR COMMUNICATION WITH HETEROGENOUS PHYSICAL LAYERS 有权
    用于与异质物理层通信的装置，系统和方法

    公开(公告)号：US20140281108A1

    公开(公告)日：2014-09-18

    申请号：US13844280

    申请日：2013-03-15

    申请人： Akshay G. Pethe ,  Mahesh Wagh ,  Manjari Kulkarni

    发明人： Akshay G. Pethe ,  Mahesh Wagh ,  Manjari Kulkarni

    IPC分类号： G06F13/40

    CPC分类号： G06F13/4282 ,  G06F13/4027 ,  Y02D10/14 ,  Y02D10/151

    摘要： A device to process data packets for communication across PHY layers which are of different respective communication protocols. In an embodiment, the device includes a first protocol stack and a second protocol stack which are each for a PCIe™ communication protocol. The first protocol stack and a second protocol stack may interface, respectively, with a first physical (PHY) layer and a second PHY layer of the device. The first protocol stack and the second protocol stack may exchange packets to facilitate communications via both the first PHY layer and the second PHY layer. In another embodiment, the first PHY layer is for communication according to the PCIe™ communication protocol and the second PHY layer is for communication according to another, comparatively low power communication protocol.

    摘要翻译： 用于处理数据分组以用于通过不同相应通信协议的PHY层进行通信的设备。 在一个实施例中，该设备包括第一协议栈和第二协议栈，它们各自用于PCIe TM通信协议。 第一协议栈和第二协议栈可分别与设备的第一物理（PHY）层和第二PHY层接口。 第一协议栈和第二协议栈可以交换分组以促进通过第一PHY层和第二PHY层的通信。 在另一个实施例中，第一PHY层用于根据PCIe TM通信协议进行通信，第二PHY层用于根据另一种较低功率通信协议进行通信。

    Providing A Load/Store Communication Protocol With A Low Power Physical Unit
    67.
    发明申请
    Providing A Load/Store Communication Protocol With A Low Power Physical Unit 审中-公开
    提供具有低功耗物理单元的加载/存储通信协议

    公开(公告)号：US20140173164A1

    公开(公告)日：2014-06-19

    申请号：US14186677

    申请日：2014-02-21

    申请人： Sridharan Ranganathan ,  Mahesh Wagh ,  David J. Harriman

    发明人： Sridharan Ranganathan ,  Mahesh Wagh ,  David J. Harriman

    IPC分类号： G06F13/38

    CPC分类号： G06F13/385 ,  G06F13/40 ,  H04L49/109

    摘要： In one embodiment, a converged protocol stack can be used to unify communications from a first communication protocol to a second communication protocol to provide for data transfer across a physical interconnect. This stack can be incorporated in an apparatus that includes a protocol stack for a first communication protocol including transaction and link layers, and a physical (PHY) unit coupled to the protocol stack to provide communication between the apparatus and a device coupled to the apparatus via a physical link. This PHY unit may include a physical unit circuit according to the second communication protocol. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，可以使用融合协议栈来将通信从第一通信协议统一到第二通信协议，以提供跨物理互连的数据传输。 该堆叠可以并入包括用于包括交易和链路层的第一通信协议的协议栈的装置，以及耦合到协议栈的物理（PHY）单元，以在设备和耦合到装置的设备之间通信 一个物理链接。 该PHY单元可以包括根据第二通信协议的物理单元电路。 描述和要求保护其他实施例。

    Integrating Non-Peripheral Component Interconnect (PCI) Resources Into A Computer System
    69.
    发明申请
    Integrating Non-Peripheral Component Interconnect (PCI) Resources Into A Computer System 有权
    将非外围组件互连（PCI）资源集成到计算机系统中

    公开(公告)号：US20130297843A1

    公开(公告)日：2013-11-07

    申请号：US13891501

    申请日：2013-05-10

    申请人： Arvind Mandhani ,  Woojong Han ,  Ken Shoemaker ,  Madhu Athreya ,  Mahesh Wagh ,  Shreekant S. Thakkar

    发明人： Arvind Mandhani ,  Woojong Han ,  Ken Shoemaker ,  Madhu Athreya ,  Mahesh Wagh ,  Shreekant S. Thakkar

    IPC分类号： G06F13/42

    CPC分类号： G06F13/4022 ,  G06F13/4027 ,  G06F13/404 ,  G06F13/4045 ,  G06F13/42

    摘要： In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，本发明包括具有根据个人计算机（PC）协议和第二协议进行通信的适配器的装置。 耦合到适配器的第一接口是对从适配器的上游接收的事务执行地址转换和排序。 第一个接口依次耦合到异构资源，每个资源包括知识产权（IP）核心和垫片，其中垫片将为IP核实现PC协议的头部，以使其能够并入设备中而无需 修改。 描述和要求保护其他实施例。

    Optimized link training and management mechanism
    70.
    发明授权
    Optimized link training and management mechanism 有权

    公开(公告)号：US08437343B1

    公开(公告)日：2013-05-07

    申请号：US13477310

    申请日：2012-05-22

    申请人： Mahesh Wagh ,  David J. Harriman

    发明人： Mahesh Wagh ,  David J. Harriman

    IPC分类号： H04L12/50 ,  H04Q11/00 ,  G06F13/00

    CPC分类号： G06F13/4282 ,  G06F1/3253 ,  G06F13/385 ,  H04Q2213/13003 ,  Y02D10/151 ,  Y02D50/20

    摘要： In one embodiment, a converged protocol stack can be used to unify communications from a first communication protocol to a second communication protocol to provide for data transfer across a physical interconnect. This stack can be incorporated in an apparatus that includes a protocol stack for a first communication protocol including transaction and link layers, and a physical (PHY) unit coupled to the protocol stack to provide communication between the apparatus and a device coupled to the apparatus via a physical link. This PHY unit may include a physical unit circuit according to the second communication protocol. Other embodiments are described and claimed.