公开(公告)号：US07608896B2

公开(公告)日：2009-10-27

申请号：US11857197

申请日：2007-09-18

申请人： Reika Ichihara ,  Yoshinori Tsuchiya ,  Hiroki Tanaka ,  Masato Koyama

发明人： Reika Ichihara ,  Yoshinori Tsuchiya ,  Hiroki Tanaka ,  Masato Koyama

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L23/62

CPC分类号： H01L21/823842 ,  H01L21/823864

摘要： A semiconductor device has an n-channel MIS transistor and a p-channel MIS transistor on a substrate. The n-channel MIS transistor includes a p-type semiconductor region formed on the substrate, a lower layer gate electrode which is formed via a gate insulating film above the p-type semiconductor region and which is one monolayer or more and 3 nm or less in thickness, and an upper layer gate electrode which is formed on the lower layer gate electrode, whose average electronegativity is 0.1 or more smaller than the average electronegativity of the lower layer gate electrode. The p-channel MIS transistor includes an n-type semiconductor region formed on the substrate and a gate electrode which is formed via a gate insulating film above the n-type semiconductor region and is made of the same metal material as that of the upper layer gate electrode.

摘要翻译： 半导体器件在衬底上具有n沟道MIS晶体管和p沟道MIS晶体管。 n沟道MIS晶体管包括形成在基板上的p型半导体区域，通过p型半导体区域上方的栅极绝缘膜形成并且为单层以上且3nm以下的下层栅电极 以及形成在下层栅电极上的上层栅电极，其平均电负性比下层栅电极的平均电负性小0.1或更小。 p沟道MIS晶体管包括形成在衬底上的n型半导体区域和通过n型半导体区域上方的栅极绝缘膜形成并由与上层相同的金属材料制成的栅电极 栅电极。

公开(公告)号：US07576397B2

公开(公告)日：2009-08-18

申请号：US11841757

申请日：2007-08-20

申请人： Reika Ichihara ,  Yoshinori Tsuchiya ,  Masato Koyama ,  Akira Nishiyama

发明人： Reika Ichihara ,  Yoshinori Tsuchiya ,  Masato Koyama ,  Akira Nishiyama

IPC分类号： H01L27/092

CPC分类号： H01L21/823857 ,  H01L21/823462

摘要： A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.

摘要翻译： 半导体器件包括半导体衬底，形成在衬底上的nMISFET，nMISFET包括形成在衬底上的第一电介质和形成在第一电介质上的第一金属栅极，并由选自Ti，Zr，Hf， Ta，Sc，Y，镧系元素和锕系和选自所述一种金属元素的硼化物，硅化物和锗化合物的一种，以及形成在所述衬底上的pMISFET，所述pMISFET包括形成在所述衬底上的第二电介质和第二金属 栅电极形成在第二电介质上并由与第一金属栅电极相同的材料制成，第二电介质面向第二金属栅电极的至少一部分由绝缘材料制成，绝缘材料与至少一部分 的第一电介质面向第一金属栅电极。

公开(公告)号：US20090072331A1

公开(公告)日：2009-03-19

申请号：US12232079

申请日：2008-09-10

申请人： Masato Koyama ,  Reika Ichihara ,  Yoshinori Tsuchiya ,  Yuuchi Kamimuta ,  Akira Nishiyama

发明人： Masato Koyama ,  Reika Ichihara ,  Yoshinori Tsuchiya ,  Yuuchi Kamimuta ,  Akira Nishiyama

IPC分类号： H01L29/78

CPC分类号： H01L21/823842

摘要： A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.

公开(公告)号：US07429777B2

公开(公告)日：2008-09-30

申请号：US11329228

申请日：2006-01-11

申请人： Yoshinori Tsuchiya ,  Masato Koyama

发明人： Yoshinori Tsuchiya ,  Masato Koyama

IPC分类号： H01L29/49

CPC分类号： H01L29/4958 ,  H01L21/2807 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/665

摘要： A semiconductor device includes a semiconductor substrate having a semiconductor layer, a gate electrode, a source region, a drain region, an element separation insulating film layer and a wiring. The gate electrode include a laminated structure having a gate insulating film formed on the semiconductor layer, a metal or a metallic compound formed on the gate insulating film and a polycrystalline silicon layer formed on the metal or metallic compound. The source region and drain region are formed on a surface portion of the semiconductor substrate and sandwich the gate electrode therebetween. The element separation insulating film layer surrounds the semiconductor layer. The wiring is in contact with the metal or metallic compound of the gate electrode.

摘要翻译： 半导体器件包括具有半导体层，栅电极，源极区，漏极区，元件隔离绝缘膜层和布线的半导体衬底。 栅极包括在半导体层上形成有栅极绝缘膜的层压结构，形成在栅极绝缘膜上的金属或金属化合物以及形成在金属或金属化合物上的多晶硅层。 源极区域和漏极区域形成在半导体衬底的表面部分上，并将栅电极夹在其间。 元件分离绝缘膜层围绕半导体层。 布线与栅电极的金属或金属化合物接触。

公开(公告)号：US07416967B2

公开(公告)日：2008-08-26

申请号：US11526637

申请日：2006-09-26

申请人： Yoshinori Tsuchiya ,  Masato Koyama ,  Masahiko Yoshiki

发明人： Yoshinori Tsuchiya ,  Masato Koyama ,  Masahiko Yoshiki

IPC分类号： H01L21/3205

CPC分类号： H01L21/823835 ,  H01L27/1203 ,  H01L29/785

摘要： According to an aspect of the invention, a semiconductor device comprises: a N-channel MIS transistor comprising; a p-type semiconductor layer; a first gate insulation layer formed on the p-type semiconductor layer; a first gate electrode formed on the first gate insulation layer; and a first source-drain region formed in the p-type semiconductor layer where the first gate electrode is sandwiched along a direction of gate length. The first gate electrode comprises a crystal phase including a cubic crystal of NiSi2 which has a lattice constant of 5.39 angstroms to 5.40 angstroms.

摘要翻译： 根据本发明的一个方面，半导体器件包括：N沟道MIS晶体管，包括： p型半导体层; 形成在p型半导体层上的第一栅绝缘层; 形成在所述第一栅极绝缘层上的第一栅电极; 以及形成在p型半导体层中的第一源极 - 漏极区，其中第一栅极沿着栅极长度的方向被夹持。 第一栅电极包括晶体相，其包括具有5.39埃至5.40埃的晶格常数的NiSi 2 N 3的立方晶体。

公开(公告)号：US20080176368A1

公开(公告)日：2008-07-24

申请号：US11841817

申请日：2007-08-20

申请人： Reika Ichihara ,  Yoshinori Tsuchiya ,  Masato Koyama ,  Akira Nishiyama

发明人： Reika Ichihara ,  Yoshinori Tsuchiya ,  Masato Koyama ,  Akira Nishiyama

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/823462

摘要： A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.

摘要翻译： 半导体器件包括半导体衬底，形成在衬底上的nMISFET，nMISFET包括形成在衬底上的第一电介质和形成在第一电介质上的第一金属栅极，并由选自Ti，Zr，Hf， Ta，Sc，Y，镧系元素和锕系和选自所述一种金属元素的硼化物，硅化物和锗化合物的一种，以及形成在所述衬底上的pMISFET，所述pMISFET包括形成在所述衬底上的第二电介质和第二金属 栅电极形成在第二电介质上并由与第一金属栅电极相同的材料制成，第二电介质面向第二金属栅电极的至少一部分由绝缘材料制成，绝缘材料与至少一部分 的第一电介质面向第一金属栅电极。

公开(公告)号：US20070278558A1

公开(公告)日：2007-12-06

申请号：US11679417

申请日：2007-02-27

申请人： Masato Koyama ,  Yoshinori Tsuchiya

发明人： Masato Koyama ,  Yoshinori Tsuchiya

IPC分类号： H01L29/788 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/28273 ,  H01L21/26513 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7881

摘要： A semiconductor device includes a p-channel MIS transistor. A p-channel MIS transistor includes; an n-type semiconductor layer formed on the substrate; first source/drain regions being formed in the n-type semiconductor layer and being separated from each other; a first gate insulating film being formed on the n-type semiconductor layer between the first source/drain regions, and containing silicon, oxygen, and nitrogen, or containing silicon and nitrogen; a first gate electrode formed above the first gate insulating film; and a first interfacial layer being formed at an interface between the first gate insulating film and the first gate electrode, and containing a 13-group element. The total number of metallic bonds in the 13-group element in the interfacial layer being larger than the total number of each of oxidized, nitrided, or oxynitrided bonds in the 13-group element in the interfacial layer.

摘要翻译： 半导体器件包括p沟道MIS晶体管。 P沟道MIS晶体管包括： 在该基板上形成的n型半导体层; 第一源极/漏极区域形成在n型半导体层中并彼此分离; 第一栅极绝缘膜，形成在第一源极/漏极区域之间的n型半导体层上，并且包含硅，氧和氮，或含有硅和氮; 形成在所述第一栅极绝缘膜上方的第一栅电极; 以及在所述第一栅极绝缘膜和所述第一栅电极之间的界面处形成并且包含13族元素的第一界面层。 界面层中13组元素中的金属键总数大于界面层中13族元素中氧化，氮化或氧氮键的总数。

公开(公告)号：US20070145488A1

公开(公告)日：2007-06-28

申请号：US11461646

申请日：2006-08-01

申请人： Masato Koyama ,  Reika Ichihara ,  Yoshinori Tsuchiya ,  Yuuichi Kamimuta ,  Akira Nishiyama

发明人： Masato Koyama ,  Reika Ichihara ,  Yoshinori Tsuchiya ,  Yuuichi Kamimuta ,  Akira Nishiyama

IPC分类号： H01L29/94

CPC分类号： H01L21/823842 ,  H01L21/823835

摘要： A semiconductor device includes a substrate, a p-channel MIS transistor formed on the substrate, the p-channel MIS transistor having a first gate electrode, and an n-channel MIS transistor formed on the substrate separately from the p-channel MIS transistor, the n-channel MIS transistor having a second gate electrode. Each of the first gate electrode and the second gate electrode is formed of an alloy of Ta and C in which a mole ratio of C to Ta (C/Ta) is from 2 to 4.

摘要翻译： 半导体器件包括衬底，形成在衬底上的p沟道MIS晶体管，具有第一栅电极的p沟道MIS晶体管和与p沟道MIS晶体管分开形成在衬底上的n沟道MIS晶体管， 该n沟道MIS晶体管具有第二栅电极。 第一栅极电极和第二栅极电极由Ta和C的合金形成，其中C与Ta（C / Ta）的摩尔比为2〜4。

公开(公告)号：US20060289953A1

公开(公告)日：2006-12-28

申请号：US11390288

申请日：2006-03-28

申请人： Kiwamu Sakuma ,  Yoshinori Tsuchiya ,  Masato Koyama

发明人： Kiwamu Sakuma ,  Yoshinori Tsuchiya ,  Masato Koyama

IPC分类号： H01L29/94

CPC分类号： H01L29/4908 ,  H01L21/823842 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/785 ,  H01L29/78654

摘要： A semiconductor device includes a first semiconductor layer of a first conductivity type, a first gate insulating film, a first gate electrode and first source/drain regions. The first gate insulating film is formed on the first semiconductor layer. The first gate electrode is formed on the first gate insulating film. The first gate electrode includes crystal grains of a first metal consisting of Ru, and a second metal selected from the group consisting of W, Ni, Mo, Rh, Pd, Re Ir, and Pt. The second metal is segregated at a grain boundary between the crystal grains of the first metal. The first source/drain regions are formed in the first semiconductor layer, across the first gate insulating film from each other in a gate length direction of the first gate insulating film.

摘要翻译： 半导体器件包括第一导电类型的第一半导体层，第一栅极绝缘膜，第一栅极电极和第一源极/漏极区域。 第一栅极绝缘膜形成在第一半导体层上。 第一栅电极形成在第一栅极绝缘膜上。 第一栅电极包括由Ru组成的第一金属的晶粒和选自W，Ni，Mo，Rh，Pd，Re Ir和Pt的第二金属。 第二金属在第一金属的晶粒之间的晶界处分离。 第一源极/漏极区域在第一栅极绝缘膜的栅极长度方向上在第一半导体层中跨越第一栅极绝缘膜彼此形成。

公开(公告)号：US20060192258A1

公开(公告)日：2006-08-31

申请号：US11329228

申请日：2006-01-11

申请人： Yoshinori Tsuchiya ,  Masato Koyama

发明人： Yoshinori Tsuchiya ,  Masato Koyama

IPC分类号： H01L29/94

CPC分类号： H01L29/4958 ,  H01L21/2807 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/665

摘要： A semiconductor device includes a semiconductor substrate having a semiconductor layer, a gate electrode, a source region, a drain region, an element separation insulating film layer and a wiring. The gate electrode include a laminated structure having a gate insulating film formed on the semiconductor layer, a metal or a metallic compound formed on the gate insulating film and a polycrystalline silicon layer formed on the metal or metallic compound. The source region and drain region are formed on a surface portion of the semiconductor substrate and sandwich the gate electrode therebetween. The element separation insulating film layer surrounds the semiconductor layer. The wiring is in contact with the metal or metallic compound of the gate electrode.

摘要翻译： 半导体器件包括具有半导体层，栅电极，源极区，漏极区，元件隔离绝缘膜层和布线的半导体衬底。 栅极包括在半导体层上形成有栅极绝缘膜的层压结构，形成在栅极绝缘膜上的金属或金属化合物以及形成在金属或金属化合物上的多晶硅层。 源极区域和漏极区域形成在半导体衬底的表面部分上，并将栅电极夹在其间。 元件分离绝缘膜层围绕半导体层。 布线与栅电极的金属或金属化合物接触。