公开(公告)号：US07092864B2

公开(公告)日：2006-08-15

申请号：US09751803

申请日：2000-12-29

申请人： Wolfgang Roesner ,  Derek Edward Williams

发明人： Wolfgang Roesner ,  Derek Edward Williams

IPC分类号： G06G17/50 ,  G06F19/00 ,  G06F9/44

CPC分类号： G06F17/5022

摘要： A method, system, and data structure for overriding a signal during model simulation. An override signal port is instantiated within a model for delivering an override signal from an instrumentation entity to a signal selection means, wherein the signal selection means selects between the signal and the override signal. A signal override is declared during model simulation, and in response to the declared signal override, the override signal is selected utilizing the signal selection means.

公开(公告)号：US07039574B1

公开(公告)日：2006-05-02

申请号：US09751802

申请日：2000-12-29

申请人： Wolfgang Roesner ,  Derek Edward Williams

发明人： Wolfgang Roesner ,  Derek Edward Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A method, system, and data structure for processing and managing a simulation event during model simulation. In accordance with the present invention, a design entity identifier is associated with the simulation event within a simulation event declaration statement. The event declaration statement includes a design entity name field containing data representing an entity name of a design entity from which the simulation event is generated. Occurrences of the simulation event are evaluated within said simulation model in accordance with the design entity identifier. An instantiation identifier field may be included within the event declaration to enable hierarchical and non-hierarchical processing of the event.

摘要翻译： 一种用于在模拟模拟期间处理和管理仿真事件的方法，系统和数据结构。 根据本发明，设计实体标识符与模拟事件声明语句内的模拟事件相关联。 事件声明语句包括设计实体名称字段，其中包含表示生成仿真事件的设计实体的实体名称的数据。 根据设计实体标识符，在所述仿真模型内评估模拟事件的发生。 事件声明中可以包括一个实例化标识符字段，以实现该事件的分级和非分层处理。

公开(公告)号：US20060004556A1

公开(公告)日：2006-01-05

申请号：US10880853

申请日：2004-06-30

申请人： Bradley Nelson ,  Wolfgang Roesner ,  Derek Williams

发明人： Bradley Nelson ,  Wolfgang Roesner ,  Derek Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  Y10S707/99931 ,  Y10S707/99943 ,  Y10S707/99945

摘要： In a hardware definition language (HDL) file among one or more files, one or more design entities containing a functional portion of a digital system are specified. The one or more design entities logically contain a plurality of latches having a respective plurality of different possible latch values that each corresponds to a different configuration of the functional portion of the digital system. With one or more statements in the one or more files, a multi-level Dial tree is defined that includes a selective control Dial (SCDial) entity at an upper level that is associated with at least one design entity. The SCDial entity has a Dial input, a plurality of Dial outputs coupled to inputs of the plurality of lower level Dials, and a mapping table indicating a mapping between each of a plurality of possible input values of the Dial input and a respective one of a plurality of sets of output values for the plurality of Dial outputs. At least one set of output values in the mapping table specifies output values for fewer than all of the plurality of Dial outputs. Each specified output value reflects a setting of at least one lower level Dial, and settings of the lower level Dials reflect which of the plurality of different possible configuration values is loaded in the plurality of configuration latches.

摘要翻译： 在一个或多个文件中的硬件定义语言（HDL）文件中，指定包含数字系统的功能部分的一个或多个设计实体。 一个或多个设计实体在逻辑上包含多个具有相应多个不同可能锁存值的锁存器，每个闩锁值对应于数字系统的功能部分的不同配置。 利用一个或多个文件中的一个或多个语句，定义多级拨号树，其包括与至少一个设计实体相关联的上级的选择性控制拨号（SCDial）实体。 SCDial实体具有拨号输入，多个拨号输出耦合到多个下级拨号的输入，以及映射表，其指示拨号输入的多个可能输入值中的每一个与相应的一个 多个拨号输出的多组输出值。 映射表中的至少一组输出值指定少于所有多个拨号输出的输出值。 每个指定的输出值反映至少一个较低级别拨号的设置，并且下级拨号的设置反映多个不同的可能配置值中的哪一个被加载到多个配置锁存器中。

公开(公告)号：US06978231B2

公开(公告)日：2005-12-20

申请号：US09729465

申请日：2000-12-05

申请人： Derek Edward Williams ,  Bryan Ronald Hunt ,  Wolfgang Roesner

发明人： Derek Edward Williams ,  Bryan Ronald Hunt ,  Wolfgang Roesner

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F8/43 ,  G06F17/5022 ,  G06F17/5045

摘要： A method and program product for instrumenting a hardware description language (HDL) design entity. The design entity is created utilizing a HDL source code file within the syntax convention of a platform HDL. In accordance with the method of the present invention an instrumentation entity is described within the HDL source code file utilizing a non-conventional syntax comment such that the instrumentation entity is embedded within the design entity without being incorporated into an overall design in which the design entity is incorporated. In accordance with a second embodiment, the HDL source code file includes a description of at least one operating event within the conventional syntax of the platform HDL, and the method of the present invention further includes associating the instrumentation entity with the operating event utilizing a non-conventional syntax comment within the HDL source code file.

摘要翻译： 一种用于测量硬件描述语言（HDL）设计实体的方法和程序产品。 使用平台HDL的语法约定中的HDL源代码文件来创建设计实体。 根据本发明的方法，使用非常规语法注释在HDL源代码文件内描述仪器实体，使得仪器实体嵌入在设计实体内，而不被并入整体设计中，其中设计实体 被纳入。 根据第二实施例，HDL源代码文件包括平台HDL的常规语法中的至少一个操作事件的描述，并且本发明的方法还包括：使用非标准语言来将检测实体与操作事件相关联， HDL源代码文件中的常规语法注释。

公开(公告)号：US20050224888A1

公开(公告)日：2005-10-13

申请号：US11116139

申请日：2005-04-27

申请人： Andrew Graham ,  Franz Hofmann ,  Wolfgang Honlein ,  Johannes Kretz ,  Franz Kreupl ,  Erhard Landgraf ,  Richard Luyken ,  Wolfgang Roesner ,  Thomas Schulz ,  Michael Specht

发明人： Andrew Graham ,  Franz Hofmann ,  Wolfgang Honlein ,  Johannes Kretz ,  Franz Kreupl ,  Erhard Landgraf ,  Richard Luyken ,  Wolfgang Roesner ,  Thomas Schulz ,  Michael Specht

IPC分类号： G11C13/02 ,  H01L29/78 ,  H01L51/00 ,  H01L51/30 ,  H01L29/76

CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C2213/17 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0512

摘要： Integrated circuit array having field effect transistors (FETs) formed next to and/or above one another. The array has a substrate, a planarized first wiring plane with interconnects and first source/drain regions of the FETs, a planarized first insulator layer on the first wiring plane, a planarized gate region layer, which has patterned gate regions made of electrically conductive material and insulator material introduced therebetween, on the first insulated layer, a planarized second insulator layer on the gate region layer, holes formed through the second insulator layer, the gate regions, and the first insulator layer, a vertical nanoelement serving as a channel region in each of the holes, a second wiring plane with interconnects and second source/drain regions of the FETs, each nanoelement being arranged between the first and second wiring planes, and a gate insulating layer between the respective vertical nanoelement and the electrically conductive material of the gate regions.

摘要翻译： 集成电路阵列具有形成在彼此之上和/或彼此之上的场效应晶体管（FET）。 阵列具有衬底，具有互连的平坦化的第一布线面和FET的第一源极/漏极区，在第一布线平面上的平坦化的第一绝缘体层，平坦化的栅极区域层，其具有由导电材料制成的图案化栅极区域 和介于其间的绝缘体材料，在所述第一绝缘层上，在所述栅极区域层上的平坦化的第二绝缘体层，穿过所述第二绝缘体层，所述栅极区域和所述第一绝缘体层形成的空穴，用作所述沟道区域中的沟道区域的垂直纳米元件 每个孔，具有互连的第二布线面和FET的第二源极/漏极区，每个纳米元件布置在第一和第二布线平面之间，并且在相应的垂直纳米元件和导电材料之间的栅极绝缘层 门区域。

公开(公告)号：US20050149313A1

公开(公告)日：2005-07-07

申请号：US10749607

申请日：2003-12-31

申请人： Wolfgang Roesner ,  Derek Williams

发明人： Wolfgang Roesner ,  Derek Williams

IPC分类号： G01R31/3183 ,  G06F9/45

CPC分类号： G01R31/318364

摘要： In a method of compiling a simulation model of a digital design, a compiler receives an indication of a desired set of instrumentation entities to be included within a simulation model of a digital design described by a plurality of hierarchically arranged design entities. The instrumentation entities monitor logical operation of one or more of the plurality of design entities during simulation for occurrence of events of interest. In response to the indication, the compiler determines by reference to a bill-of-materials of a previously compiled file whether or not the previously compiled file was compiled with instrumentation entities compatible with the desired set of instrumentation entities. In response to determining that the previously compiled file was compiled with compatible instrumentation entities, the compiler compiles the simulation model of the digital design utilizing the previously compiled file in accordance with the indication.

摘要翻译： 在编译数字设计的仿真模型的方法中，编译器接收要包括在由多个分层布置的设计实体描述的数字设计的仿真模型内的期望的一组仪器实体的指示。 仪器实体在仿真期间监视多个设计实体中的一个或多个设计实体的逻辑运算，用于感兴趣事件的发生。 响应于该指示，编译器通过参考先前编译的文件的材料清单来确定先前编译的文件是否是与所需的一组仪器实体兼容的仪器实体编译的。 响应于确定先前编译的文件是使用兼容的仪器实体编译的，编译器将根据指示使用先前编译的文件编译数字设计的仿真模型。

公开(公告)号：US20050100938A1

公开(公告)日：2005-05-12

申请号：US10939319

申请日：2004-09-09

申请人： Franz Hofmann ,  Richard Luyken ,  Wolfgang Roesner

发明人： Franz Hofmann ,  Richard Luyken ,  Wolfgang Roesner

IPC分类号： C12Q1/68 ,  G01N33/543

CPC分类号： G01N33/54386 ,  G01N27/3276

摘要： Vertical impedance sensor arrangement including a substrate, a first electrically conductive structure having a first uncovered surface and being arranged in and/or on the substrate, a spacer arranged above the substrate and/or at least partially on the first electrically conductive structure, a second electrically conductive structure having a second uncovered surface and being arranged on the spacer, and capture molecules, which are immobilized on the first and on the second uncovered surface, are set up such that particles to be detected hybridize with the capture molecules. The spacer is formed separately from the substrate, and the thickness of the spacer is defined by means of a deposition method.

摘要翻译： 垂直阻抗传感器布置包括基底，具有第一未覆盖表面并布置在基底中和/或基底上的第一导电结构，布置在基底上和/或至少部分地在第一导电结构上的间隔物，第二 具有第二未覆盖表面并布置在间隔物上的导电结构，并且被固定在第一和第二未覆盖表面上的捕获分子被设置成使得待检测的颗粒与捕获分子杂交。 间隔物与衬底分开形成，并且通过沉积方法限定间隔物的厚度。

公开(公告)号：US20050049842A1

公开(公告)日：2005-03-03

申请号：US10651156

申请日：2003-08-28

申请人： Wolfgang Roesner ,  Derek Williams

发明人： Wolfgang Roesner ,  Derek Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A method, data processing system, and program product for building an instrumented simulation model of a digital design are disclosed. According to the method, a model build tool locates, within design data collectively defining a simulation model of the digital design, a definition of a configuration construct specifying a relationship between values of one or more configuration latches within the digital design and settings of the configuration construct. In response to locating the definition of the configuration construct, the model build tool automatically creates an instrumentation entity within the design data. The instrumentation entity has one or more inputs logically coupled to the one or more configuration latches and one or more outputs for providing signals indicating characteristics of the configuration construct during simulation.

摘要翻译： 公开了一种用于构建数字设计仪表化仿真模型的方法，数据处理系统和程序产品。 根据该方法，模型构建工具在设计数据中共同定义数字设计的仿真模型，定义了指定数字设计中的一个或多个配置锁存器的值与配置设置之间的关系的配置结构 构造。 响应定位配置结构的定义，模型构建工具会自动在设计数据中创建一个检测实体。 仪器实体具有逻辑上耦合到一个或多个配置锁存器和一个或多个输出的一个或多个输入，用于在模拟期间提供指示配置结构特征的信号。

公开(公告)号：US06750095B1

公开(公告)日：2004-06-15

申请号：US09787966

申请日：2001-05-29

申请人： Emmerich Bertagnoll ,  Franz Hofmann ,  Bernd Goebel ,  Wolfgang Roesner

发明人： Emmerich Bertagnoll ,  Franz Hofmann ,  Bernd Goebel ,  Wolfgang Roesner

IPC分类号： H01L218242

CPC分类号： H01L27/10876 ,  H01L27/1052 ,  H01L27/10823 ,  H01L27/112 ,  H01L27/11273

摘要： A method of producing an integrated circuit having a vertical MOS transistor includes doping a substrate to form a layer adjacent to its surface and forming a lower doped layer serving as the transistor's first source/drain region. The transistor's channel region is formed by doping a central layer above the lower layer. A second source/drain region is formed by doping an upper layer above the central layer. The upper, central and lower layers form a layer sequence having opposed first and second faces. A connecting structure is formed on the first face to electrically connect the channel region and the substrate. The connecting structure laterally adjoins at least the central layer and the lower layer, and extends into the substrate. A gate dielectric and adjacent gate electrode are formed on the second face.

摘要翻译： 制造具有垂直MOS晶体管的集成电路的方法包括：掺杂衬底以形成与其表面相邻的层，并形成用作晶体管的第一源极/漏极区的下掺杂层。 晶体管的沟道区域通过在下层上掺杂中心层而形成。 通过在中心层上方掺杂上层形成第二源/漏区。 上层，中层和下层形成具有相对的第一和第二面的层序列。 在第一面上形成连接结构，以电连接沟道区和衬底。 连接结构至少横向邻接中心层和下层，并延伸到基底中。 在第二面上形成栅电介质和相邻栅电极。

公开(公告)号：US06470478B1

公开(公告)日：2002-10-22

申请号：US09345163

申请日：1999-06-29

申请人： John Fowler Bargh ,  Wolfgang Roesner ,  Derek Edward Williams

发明人： John Fowler Bargh ,  Wolfgang Roesner ,  Derek Edward Williams

IPC分类号： G06F1750

CPC分类号： G01R31/318357 ,  G01R31/31704 ,  G06F17/5022

摘要： A method and system that utilize the expressiveness of hardware description languages for efficiently and comprehensively monitoring performance characteristics of a digital circuit design during simulation. According to the present invention, a design entity that is part of a digital circuit design is first described utilizing a hardware description language. Next, a counting instrument is described utilizing the same hardware description language. The counting instrument is designed to detect occurrences of a count event within the design entity during simulation of the digital circuit design. The counting instrument is associated with the design entity utilizing a non-conventional call, such that the counting instrument may be utilized to monitor each instantiation of the design entity within the simulation model without the instrumentation entity becoming incorporated into the digital circuit design. In association with the counting instrument, a linear feedback shift register is automatically generated for recording the number of occurrences of the count event within the design entity.

摘要翻译： 一种利用硬件描述语言表达的方法和系统，用于在模拟期间高效全面地监测数字电路设计的性能特征。 根据本发明，首先使用硬件描述语言描述作为数字电路设计的一部分的设计实体。 接下来，使用相同的硬件描述语言来描述计数仪器。 计数仪器被设计为在模拟数字电路设计期间检测设计实体内的计数事件的发生。 计数仪器与设计实体相关联，利用非传统调用，使得计数仪器可用于监视模拟模型内的设计实体的每个实例化，而不需要将仪器实体纳入数字电路设计。 与计数仪器相关联，自动生成线性反馈移位寄存器，用于记录设计实体内计数事件的发生次数。