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公开(公告)号：US20210264960A1
公开(公告)日：2021-08-26
申请号：US17196650
申请日：2021-03-09
Applicant: Micron Technology, Inc.
Inventor： Richard E. Fackenthal , Daniele Vimercati , Duane R. Mills
Abstract: Methods, systems, and devices related to wear leveling for random access and ferroelectric memory are described. Non-volatile memory devices, e.g., ferroelectric random access memory (FeRAM) may utilize wear leveling to extend life time of the memory devices by avoiding reliability issues due to a limited cycling capability. A wear-leveling pool, or number of cells used for a wear-leveling application, may be expanded by softening or avoiding restrictions on a source page and a destination page within a same section of memory array. In addition, error correction code may be applied when moving data from the source page to the destination page to avoid duplicating errors present in the source page.
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公开(公告)号：US11003361B2
公开(公告)日：2021-05-11
申请号：US16752959
申请日：2020-01-27
Applicant: Micron Technology, Inc.
Inventor： Richard E. Fackenthal , Duane R. Mills
Abstract: In an example, a portion of a memory array may be selected to be wear leveled based on how often the portion is or is to be accessed. The portion may be wear leveled.
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公开(公告)号：US20200059252A1
公开(公告)日：2020-02-20
申请号：US16104470
申请日：2018-08-17
Applicant: Micron Technology, Inc.
Inventor： Richard E. Fackenthal
Abstract: Methods, systems, and devices for operating memory cell(s) using an enhanced bit flipping scheme are described. An enhanced bit flipping scheme may include methods, systems, and devices for performing error correction of data bits in a codeword concurrently with the generation of a flip bit that indicates whether data bits in a corresponding codeword are to be flipped; for refraining from performing error correction of inversion bit(s) in the codeword; and for generating a high-reliability flip bit using multiple inversion bits. For instance, a flip bit that is even more reliable may be generated by determining whether a number of, a majority of, or all of the inversion bits indicate that the data bits are in an inverted state.
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公开(公告)号：US10528099B2
公开(公告)日：2020-01-07
申请号：US15289350
申请日：2016-10-10
Applicant: Micron Technology, Inc.
Inventor： Richard E. Fackenthal
Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells and, more particularly, a temperature update for a memory device are described. A memory array may be operated according to a timing cycle that includes a first interval for performing a first type of operation and a second interval for performing a second type of operation, where a duration of the first interval is greater than a duration of the second type of interval. A temperature related to a temperature of at least a portion of the memory array may be sampled during an interval of the second type, and the memory array may be reconfigured based at least in part on a sampled temperature. The first type of operation may then be performed on a reconfigured memory array during an interval of the first type.
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公开(公告)号：US10431281B1
公开(公告)日：2019-10-01
申请号：US16104711
申请日：2018-08-17
Applicant: Micron Technology, Inc.
Inventor： Richard E. Fackenthal , Daniele Vimercati , Jahanshir Javanifard
IPC: G11C11/22
Abstract: Methods, systems, and devices for section-based data protection in a memory device are described. In one example, a memory device may include a set memory sections each having memory cells configured to be selectively coupled with access lines of the respective memory section. A method of operating the memory device may include selecting at least one of the sections for a voltage adjustment operation based on a determined value of a timer, and performing the voltage adjustment operation on the selected section by activating each of a plurality of word lines of the selected section. The voltage adjustment operation may include applying an equal voltage to opposite terminals of the memory cells, which may allow built-up charge, such as leakage charge accumulating from access operations of the selected memory section, to dissipate from the memory cells of the selected section.
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Patent Agency Ranking
公开(公告)号：US10416903B2
公开(公告)日：2019-09-17
申请号：US16102807
申请日：2018-08-14
Applicant: Micron Technology, Inc.
Inventor： Richard E. Fackenthal , Duane R. Mills
Abstract: In an example, a portion of a memory array may be selected to be wear leveled based on how often the portion is or is to be accessed. The portion may be wear leveled.
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公开(公告)号：US10403388B2
公开(公告)日：2019-09-03
申请号：US15913413
申请日：2018-03-06
Applicant: Micron Technology, Inc.
Inventor： Richard E. Fackenthal , Charles L. Ingalls
Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways depending, for example, on a relationship between cell plates of the group of cells. Cells may be selected in pairs in order to accommodate an electric current relationship, such as a short, between cells that make up the pair. Cells may be arranged in cell plate groups, and a pair of cells may include a first cell plate from one cell plate group and a second cell plate from the same cell plate group or from another, adjacent cell plate group. So a pair of cell plates may include cell plates from different cell plate groups. The first and second cell plates may be selected as a pair or a group based at least in part on the electric current relationship between the cell plates.
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公开(公告)号：US10388352B2
公开(公告)日：2019-08-20
申请号：US15855643
申请日：2017-12-27
Applicant: Micron Technology, Inc.
Inventor： Richard E. Fackenthal
IPC: G11C11/22
Abstract: A memory device having a plurality sections of memory cells, such as ferroelectric memory cells may provide for concurrent access to memory cells within independent sections of the memory device. A first memory cell may be activated, and it may be determined that a second memory cell is independent of the first memory cell. If the second memory cell is independent of the first memory cell, the second memory cell may be activated prior to the conclusion of operations at the first memory cell. Latching hardware at memory sections may latch addresses at the memory sections in order to allow a new address to be provided to a different section to access the second memory cell.
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公开(公告)号：US20190042107A1
公开(公告)日：2019-02-07
申请号：US15669290
申请日：2017-08-04
Applicant: Micron Technology, Inc.
Inventor： Richard E. Fackenthal , Duane R. Mills
Abstract: In an example, a portion of a memory array may be selected to be wear leveled based on how often the portion is or is to be accessed. The portion may be wear leveled.
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公开(公告)号：US20180101204A1
公开(公告)日：2018-04-12
申请号：US15289350
申请日：2016-10-10
Applicant: Micron Technology, Inc.
Inventor： Richard E. Fackenthal
CPC classification number: G06F1/206 , G06F3/061 , G06F3/0634 , G06F3/0653 , G06F3/0659 , G06F3/0679 , G06F3/0688 , Y02D10/16
Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells and, more particularly, a temperature update for a memory device are described. A memory array may be operated according to a timing cycle that includes a first interval for performing a first type of operation and a second interval for performing a second type of operation, where a duration of the first interval is greater than a duration of the second type of interval. A temperature related to a temperature of at least a portion of the memory array may be sampled during an interval of the second type, and the memory array may be reconfigured based at least in part on a sampled temperature. The first type of operation may then be performed on a reconfigured memory array during an interval of the first type.
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