公开(公告)号：US11093385B2

公开(公告)日：2021-08-17

申请号：US16697724

申请日：2019-11-27

申请人： Micron Technology, Inc.

发明人： Kishore Kumar Muchherla ,  Peter Feeley ,  Ashutosh Malshe ,  Daniel J. Hubbard ,  Christopher S. Hale ,  Kevin R. Brandt ,  Sampath K. Ratnam ,  Yun Li ,  Marc S. Hamilton

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F12/0891 ,  G06F3/06 ,  G06F12/06 ,  G11C11/56

摘要： A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: select a garbage collection (GC) source block storing valid data, and designate a storage mode for an available memory block based on the valid data, wherein the storage mode is for configuring memory cells in the available memory block as cache memory that stores a number of bits less than maximum storage capacities thereof for subsequent or upcoming data writes.

公开(公告)号：US20210191853A1

公开(公告)日：2021-06-24

申请号：US16726527

申请日：2019-12-24

申请人： Micron Technology, Inc.

发明人： Peng Xu ,  Jiangang Wu ,  Yun Li

IPC分类号： G06F12/02 ,  G06F12/0882 ,  G06F12/0873 ,  G06F1/3234 ,  G11C11/408

摘要： A media management operation to write data from a source block of a cache memory to a set of pages of a destination block of a storage area of a memory sub-system that is at a higher data density than the cache memory a write request to program data to a memory device of a memory sub-system is executed. An entry of a first data structure identifying a page count corresponding to the source block of the cache memory is generated. Following a determination that the data is written to the set of pages of the destination block of the storage area, the entry is updated to identify a decreased page count corresponding to the source block, where the data is erased from the source block when the decreased page count satisfies a condition. A second entry of a second data structure including information mapping a logical block to the source block of the cache memory is also updated.

公开(公告)号：US20210181966A1

公开(公告)日：2021-06-17

申请号：US16715986

申请日：2019-12-16

申请人： Micron Technology, Inc.

发明人： Peng Xu ,  Jiangang Wu ,  Yun Li

IPC分类号： G06F3/06 ,  G06F12/1009

摘要： A write request to program data to a memory device of a memory sub-system is received. An intermediate entry of a data structure is generated, the intermediate entry including a pointer identifying a write buffer associated with an intermediate write operation corresponding to the write request. A read request to read the data from the memory device is received and a look-up operation of the data structure is performed to identify the intermediate entry. Using the pointer to locate the write buffer associated with the intermediate write operation. The write buffer is copied to a read buffer associated with the read request and the read request is executed using the read buffer.

公开(公告)号：US10223259B1

公开(公告)日：2019-03-05

申请号：US15693153

申请日：2017-08-31

申请人： Micron Technology, Inc.

发明人： Yun Li ,  Kishore Kumar Muchherla ,  Peter Feeley ,  Ashutosh Malshe ,  Daniel J. Hubbard ,  Christopher S. Hale ,  Kevin R. Brandt ,  Sampath K. Ratnam

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F12/0891

摘要： A memory system includes: a memory array including a plurality of memory cells, the plurality of memory cells including a plurality of cache memory cells; and a controller coupled to the memory array, the controller configured to: track usage of a first subset of the plurality of cache memory cells operating in a single-level cell (SLC) mode, wherein the tracking includes monitoring for an idle time event; and designate a storage mode for a second subset of the plurality of cache memory cells based on the tracked usage of the first subset, wherein the storage mode determines a storage density to be used for data writes.