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公开(公告)号：US11411749B2
公开(公告)日：2022-08-09
申请号：US16778442
申请日：2020-01-31
Applicant: NXP B.V.
Inventor： Jan-Peter Schat
IPC: H04L29/06 , H04L9/32 , H03K3/037 , H03K19/003 , G06F21/74
Abstract: A tie cell includes a first flip-flop having a physically unclonable function (PUF), a second flip-flop that generates a PUF key value, and logic that logically combines the PUF value and the PUF key value to generate an output signal having a constant logical value. The PUF value is based on a power-up value stored in the first flip-flop, which power-up value is generated based on physical and/or electrical characteristics produced from a manufacturing process. The output value is generated to tie digital logic to the constant logical value.
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公开(公告)号：US11329834B2
公开(公告)日：2022-05-10
申请号：US16787566
申请日：2020-02-11
Applicant: NXP B.V.
Inventor： Jan-Peter Schat
IPC: H04L9/32 , H03K19/003
Abstract: A method for controlling access to a chip includes obtaining first values of a first physically unclonable function of the chip, obtaining second values that correspond to at least one challenge word, performing a simulation based on the first values and the second values, and generating an authentication result for the chip based on results of the simulation. The simulation may generate responses to logical operations corresponding to combinatorial logic in the chip, and the logical operations may be performed based on a predetermined sequence of the first values and the second values. The chip may be authenticated based on a match between the responses generated by the simulation and a second physically unclonable function of the chip.
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公开(公告)号：US11271722B2
公开(公告)日：2022-03-08
申请号：US16405484
申请日：2019-05-07
Applicant: NXP B.V.
Inventor： Jan-Peter Schat
Abstract: An apparatus in accordance with embodiments includes front-end radar circuitry and storage circuitry. The front-end radar circuitry generates a digital data stream that represents received radar wave signals and provides a cryptographic hash using the digital data stream, timing information, and apparatus-specific data. The storage circuitry stores the digital data stream and the cryptographic hash indicative of authenticity of the digital data stream.
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公开(公告)号：US11146433B2
公开(公告)日：2021-10-12
申请号：US16815258
申请日：2020-03-11
Applicant: NXP B.V.
Inventor： Jan-Peter Schat
IPC: H04L27/04 , H04B1/69 , H04B7/0456
Abstract: A method for high data rate transmission using minimum energy coding with Ultra Wide Band modulation includes encoding each of a plurality of sourcewords into a respective codeword. Each respective codeword includes a single logic-high bit. A codeword duty cycle is less than a low duty cycle threshold, wherein the codeword duty cycle is based on a bit length of the codeword. Each respective codeword is modulated with an On-Off-Keying (OOK) modulation to form a respective modulated codeword, wherein a transmission of each modulated codeword occurs only for the single logic-high bit in each respective codeword.
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公开(公告)号：US11145340B2
公开(公告)日：2021-10-12
申请号：US16837368
申请日：2020-04-01
Applicant: NXP B.V.
Inventor： Jan-Peter Schat
IPC: G11C7/22 , G01R31/317 , G01R31/3177 , G11C7/10 , H04L12/26
Abstract: A data transmission interface for use in a first integrated circuit, for encoding and sending a data packet from the first IC to a second IC via a data bus having three data wires, the data transmission interface being arranged to generate three time-dependent binary signals which jointly encode the data packet, each of the signals being associated with a unique data wire of the data bus and spanning a temporal cycle T within which are defined six consecutive time stamps T1 . . . T6 at which the signals are allowed to change logical state, the data transmission interface further arranged to transmit the signals to the second IC substantially in parallel on their respective data wires, wherein, irrespective of the data packet content: at each time stamp T1 . . . T6 exactly one of the signals changes logical state; each signal changes logical state twice during the cycle; and in the first half of the cycle, all signals change from a logical low state to a logical high state or all signals change from a logical high state to a logical low state.
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Patent Agency Ranking
公开(公告)号：US20210288849A1
公开(公告)日：2021-09-16
申请号：US16815258
申请日：2020-03-11
Applicant: NXP B.V.
Inventor： Jan-Peter Schat
IPC: H04L27/04 , H04B7/0456 , H04B1/69
Abstract: A method for high data rate transmission using minimum energy coding with Ultra Wide Band modulation includes encoding each of a plurality of sourcewords into a respective codeword. Each respective codeword includes a single logic-high bit. A codeword duty cycle is less than a low duty cycle threshold, wherein the codeword duty cycle is based on a bit length of the codeword. Each respective codeword is modulated with an On-Off-Keying (OOK) modulation to form a respective modulated codeword, wherein a transmission of each modulated codeword occurs only for the single logic-high bit in each respective codeword.
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公开(公告)号：US11112458B1
公开(公告)日：2021-09-07
申请号：US16999419
申请日：2020-08-21
Applicant: NXP B.V.
Inventor： Jan-Peter Schat
IPC: G01R31/3177 , G01R31/3185 , G01R31/317 , H03K3/037 , H03K19/20
Abstract: During a test for integrated circuit aging effects, contents of a first set of flip flop circuits are transferred to a second set of flip flop circuits. A first test value is applied to inputs of a combinatorial logic circuit and outputs from the combinatorial logic circuitry are provided to inputs of the first set of flip flop circuits. The combinatorial logic circuitry is reversible and conservative. The outputs from the first flip flop circuits are compared to the first test value to determine if there is a match. A second test value is applied to the inputs of the combinatorial logic circuitry and the outputs from the combinatorial logic circuitry are provided to inputs of the first set of flip flop circuits. The outputs from the first flip flop circuits are compared to the second test value to determine if there is a match, and when the test mode finishes, contents of the second set of flip flop circuits are transferred to the first set of flip flop circuits.
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公开(公告)号：US10955528B2
公开(公告)日：2021-03-23
申请号：US16119083
申请日：2018-08-31
Applicant: NXP B.V.
Inventor： Abdellatif Zanati , Jan-Peter Schat
Abstract: A built-in self-test, BIST, radar unit (100) is described. The BIST radar unit (100) comprises: a frequency generation circuit (110) configured to generate a mmW transmit signal; a transmitter circuit comprising: at least one phase shifter (130, 132) configured apply at least one phase shift to the mmW transmit signal; and at least one phase inverter (140, 142) coupled to the at least one phase shifter (130, 132) and configured to invert a phase of the phase shifted mmW transmit signal. A receiver configured to receive and process a received version of the mmW transmit signal. The at least one phase inverter (140, 142) is configured to rotate the phase shifted mmW transmit signal to apply a secondary modulation to the mmW transmit signal; and the receiver is configured to receive and process a received version of the mmW transmit signal to determine an operational state of the BIST radar unit (100) based on a determined phase shift performance of the secondary modulation of the received version of the mmW transmit signal.
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公开(公告)号：US20210050068A1
公开(公告)日：2021-02-18
申请号：US16542776
申请日：2019-08-16
Applicant: NXP B.V.
Inventor： Jan-Peter Schat
Abstract: Embodiments combine error correction code (ECC) and transparent memory built-in self-test (TMBIST) for memory fault detection and correction. An ECC encoder receives input data and provides ECC data for data words stored in memory. Input XOR circuits receive the input data and output XOR'ed data as payload data for the data words. Output XOR circuits receive the payload data and output XOR'ed data. An ECC decoder receives the ECC data and the XOR'ed output data and generates error messages. Either test data from a controller running a TMBIST process or application data from a processor executing an application is selected as the input data. Either test address/control signals from the controller or application address/control signals from the processor are selected for memory access. During active operation of the application, memory access is provided to the processor and the controller, and the memory is tested during the active operation.
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公开(公告)号：US10853485B2
公开(公告)日：2020-12-01
申请号：US16004521
申请日：2018-06-11
Applicant: NXP B.V.
Inventor： Jan-Peter Schat , Michael Johannes Döscher
IPC: G06F21/55 , G01R31/3185 , G06F21/76
Abstract: Certain aspects of the disclosure are directed to methods and apparatuses of intrusion detection for integrated circuits. An example apparatus can include a wired communications bus configured and arranged to carry data and a plurality of integrated circuits. The plurality of integrated circuits can include a first integrated circuit configured and arranged to operate in a scan mode during which the first integrated circuit performs a scan test to detect one or more faults in circuitry of the plurality of integrated circuits. The plurality of integrated circuits can further include a second integrated circuit configured and arranged to operate in a mission mode and supervise data traffic by monitoring communications including data patterns and accesses on the wired communications bus. In response to identifying a suspected illegitimate access, the second integrated circuit can perform a security action to mitigate a suspect illegitimate action in the plurality of integrated circuits.
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