公开(公告)号：US07093208B2

公开(公告)日：2006-08-15

申请号：US10842589

申请日：2004-05-10

申请人： Patrick M. Williams ,  Ee K. Cho ,  David J. Hathaway ,  Mei-Ting Hsu ,  Lawrence K. Lange ,  Gregory A. Northrop ,  Chandramouli Visweswariah ,  Cindy ShuiKing Washburn ,  Jun Zhou

发明人： Patrick M. Williams ,  Ee K. Cho ,  David J. Hathaway ,  Mei-Ting Hsu ,  Lawrence K. Lange ,  Gregory A. Northrop ,  Chandramouli Visweswariah ,  Cindy ShuiKing Washburn ,  Jun Zhou

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A Digital Design Method which may be automated is for obtaining timing closure in the design of large, complex, high-performance digital integrated circuits. The methodincludes the use of a tuner on random logic macros that adjusts transistor sizes in a continuous domain. To accommodate this tuning, logic gates are mapped to parameterized cells for the tuning and then back to fixed gates after the tuning. Tuning is constrained in such a way as to minimize “binning errors” when the design is mapped back to fixed cells. Further, the critical sections of the circuit are marked in order to make the optimization more effective and to fit within the problem-size constraints of the tuner. A specially formulated objective function is employed during the tuning to promote faster global timing convergence, despite possibly incorrect initial timing budgets. The specially formulated objective function targets all paths that are failing timing, with appropriate weighting, rather than just targeting the most critical path. Finally, the addition of multiple threshold voltage gates allows for increased performance while limiting leakage power.

摘要翻译： 可以自动化的数字设计方法是在大型，复杂，高性能数字集成电路的设计中获得定时关闭。 该方法包括在随机逻辑宏中使用调谐器来调整连续域中的晶体管尺寸。 为了适应这种调谐，逻辑门被映射到用于调谐的参数化单元，然后在调谐之后返回到固定门。 调整受限于将设计映射回固定单元格时最小化“合并错误”。 此外，电路的关键部分被标记以便使优化更有效并且适应调谐器的问题尺寸约束。 在调整期间采用了特别制定的目标函数，以促进更快的全局时序收敛，尽管可能不正确的初始时间预算。 特别制定的目标函数针对所有失败时机的路径，以适当的权重，而不是仅针对最关键的路径。 最后，添加多个阈值电压门允许提高性能，同时限制漏电功率。

公开(公告)号：US07003747B2

公开(公告)日：2006-02-21

申请号：US10435824

申请日：2003-05-12

申请人： Jun Zhou ,  David J. Hathaway ,  Chandramouli Visweswariah ,  Patrick M. Williams

发明人： Jun Zhou ,  David J. Hathaway ,  Chandramouli Visweswariah ,  Patrick M. Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/505 ,  G06F2217/84

摘要： Disclosed is a method for enhanced efficiency and effectiveness in achieving timing closure of large, complex, high-performance digital integrated circuits. Circuit macros are re-optimized and re-tuned in the timing closure loop by means of a reformulated objective function that allows the optimizer to improve the slack of all signals rather than just the most critical one(s). The incentive to improve the timing of a sub-critical signal is a diminishing function of the criticality of the signal. Thus all signals are improved during the optimization, with the highest incentive to improve on the most critical signals, leading to faster and more effective overall timing closure.

摘要翻译： 公开了一种用于提高大型，复杂，高性能数字集成电路的定时闭合的效率和有效性的方法。 电路宏通过重新配置的目标函数在时序闭合循环中重新优化和重新调整，允许优化器改善所有信号的松弛，而不仅仅是最关键的。 改善次临界信号时序的动机是信号临界性的递减函数。 因此，在优化期间，所有信号都得到改进，最高激励措施可以改善最关键的信号，从而实现更快更有效的整体时序收敛。

公开(公告)号：US06615395B1

公开(公告)日：2003-09-02

申请号：US09467208

申请日：1999-12-20

申请人： David J. Hathaway ,  Chandramouli V. Kashyap ,  Byron L. Krauter ,  Sharad Mehrotra ,  Alexander J. Suess

发明人： David J. Hathaway ,  Chandramouli V. Kashyap ,  Byron L. Krauter ,  Sharad Mehrotra ,  Alexander J. Suess

IPC分类号： G06F1750

CPC分类号： G06F17/5031

摘要： A method for performing a static timing analysis on an integrated circuit chip or module taking into account the effect of wiring interconnection coupling is described. The wiring interactions are modeled as appropriate equivalent grounded capacitances, allowing traditional delay calculation methods to be applied. The method includes the steps of assigning a pessimistic value to the wiring coupling interaction between nets forming the integrated circuit chip; performing the static timing analysis using computed timing parameters which are a function of net capacitance, the net capacitance being based on the pessimistic value of the coupling interaction between the nets; updating the net capacitance of selected nets based on 1) an overlap between an arrival time window of each of the selected nets and a possible arrival time window of each of the other nets which are coupled to the each of selected nets, and 2) on the slew of each of the selected nets and the slew of each of the other nets which are coupled to the selected nets; and updating the static timing analysis based on the updated net capacitances of the selected nets.

摘要翻译： 描述了考虑到布线互连耦合的影响，在集成电路芯片或模块上执行静态时序分析的方法。 布线相互作用被建模为适当的等效接地电容，允许应用传统的延迟计算方法。 该方法包括以下步骤：为形成集成电路芯片的网络之间的布线耦合交互分配悲观值; 使用作为净电容的函数的计算定时参数来执行静态时序分析，净电容基于网络之间的耦合相互作用的悲观值; 基于以下步骤更新所选网络的净电容：1）每个所选网络的到达时间窗口与耦合到所选网络中的每一个网络的每个其它网络的可能到达时间窗口之间的重叠，以及2） 所选择的网络中的每一个的转换以及耦合到所选择的网络的每个其他网络的转换; 以及基于所选网络的更新的净电容来更新静态时序分析。

公开(公告)号：US06425110B1

公开(公告)日：2002-07-23

申请号：US09213675

申请日：1998-12-17

申请人： David J. Hathaway ,  Anthony D. Drumm ,  Peter J. Osler

发明人： David J. Hathaway ,  Anthony D. Drumm ,  Peter J. Osler

IPC分类号： G06F1750

CPC分类号： G06F17/505

摘要： A method for analyzing and optimizing a design, such as a circuit design, which relates to the application of at least one optimization procedure, evaluating the benefit and net cost of the optimization procedure and then through the checkpoint manager, recording and reversing changes of the design. The execution and reversal of multiple optimizations may occur in a trial mode followed by evaluation of the executed and reversed designs and then the reinstatement of the best optimization.

摘要翻译： 一种用于分析和优化诸如电路设计的设计的方法，其涉及应用至少一个优化过程，评估优化过程的益处和净成本，然后通过检查点管理器，记录和反转变化 设计。 多个优化的执行和反转可能发生在试用模式中，之后是执行和反向设计的评估，然后恢复最佳优化。

公开(公告)号：US08655634B2

公开(公告)日：2014-02-18

申请号：US12721227

申请日：2010-03-10

申请人： David J. Hathaway ,  Vasant Rao ,  Ronald D. Rose ,  Ali Sadigh ,  Jeffrey P. Soreff ,  David W. Winston

发明人： David J. Hathaway ,  Vasant Rao ,  Ronald D. Rose ,  Ali Sadigh ,  Jeffrey P. Soreff ,  David W. Winston

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/509 ,  G06F2217/84

摘要： A system, method and program product for modeling load effects of a load CCC (channel connected component) in a transistor network. A system is disclosed that includes an analysis system that determines allowable logical state and transition functions for nets in a load CCC for a transition or state of a driving CCC for which a load condition is being determined; a trace system that traverses paths in the load CCC from a set of input terminals; and an element replacement system that replaces circuit elements in the load CCC to create a modeled CCC, wherein a circuit element replacement is based on a type of circuit element encountered along a trace, and state and transition functions of nets connected to an encountered circuit element.

摘要翻译： 一种用于建模晶体管网络中负载CCC（通道连接部件）的负载影响的系统，方法和程序产品。 公开了一种系统，其包括分析系统，该分析系统确定负载CCC中针对正在确定负载条件的驱动CCC的转变或状态的网络的允许逻辑状态和转换功能; 跟踪系统，从一组输入端子遍历负载CCC中的路径; 以及元件替换系统，其替换负载CCC中的电路元件以创建建模的CCC，其中电路元件替换基于沿着跟踪遇到的电路元件的类型，以及连接到遇到的电路元件的网络的状态和转换功能 。

公开(公告)号：US20110224965A1

公开(公告)日：2011-09-15

申请号：US12721227

申请日：2010-03-10

申请人： David J. Hathaway ,  Vasant Rao ,  Ronald D. Rose ,  Ali Sadigh ,  Jeffrey P. Soreff ,  David W. Winston

发明人： David J. Hathaway ,  Vasant Rao ,  Ronald D. Rose ,  Ali Sadigh ,  Jeffrey P. Soreff ,  David W. Winston

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/509 ,  G06F2217/84

摘要： A system, method and program product for modeling load effects of a load CCC (channel connected component) in a transistor network. A system is disclosed that includes an analysis system that determines allowable logical state and transition functions for nets in a load CCC for a transition or state of a driving CCC for which a load condition is being determined; a trace system that traverses paths in the load CCC from a set of input terminals; and an element replacement system that replaces circuit elements in the load CCC to create a modeled CCC, wherein a circuit element replacement is based on a type of circuit element encountered along a trace, and state and transition functions of nets connected to an encountered circuit element.

摘要翻译： 一种用于建模晶体管网络中负载CCC（通道连接部件）的负载影响的系统，方法和程序产品。 公开了一种系统，其包括分析系统，该分析系统确定负载CCC中针对正在确定负载条件的驱动CCC的转变或状态的网络的允许逻辑状态和转换功能; 跟踪系统，从一组输入端子遍历负载CCC中的路径; 以及元件替换系统，其替换负载CCC中的电路元件以创建建模的CCC，其中电路元件替换基于沿着跟踪遇到的电路元件的类型，以及连接到遇到的电路元件的网络的状态和转换功能 。

公开(公告)号：US07987440B2

公开(公告)日：2011-07-26

申请号：US12351944

申请日：2009-01-12

申请人： Kerim Kalafala ,  Jennifer E. Basile ,  David J. Hathaway ,  Pooja M. Kotecha

发明人： Kerim Kalafala ,  Jennifer E. Basile ,  David J. Hathaway ,  Pooja M. Kotecha

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method and a system for validating clock skews during a hierarchical static timing analysis of a chip or multi-chip package. Each pair of clock inputs of a hierarchical module bounds the allowable clock skew, creating new relative constraints on clock input arrival times propagated to those clock inputs. One embodiment is based on asserted arrival times and a maximum of computed slack values at said clock inputs, while a second embodiment is based on asserted arrival times and a minimum of downstream test slack values. The method further converts module clock assertions into a set of relative timing constraints to allow a hierarchical timing sign-off even in circumstances where absolute timing arrivals are not totally known at the time of module analysis.

摘要翻译： 一种用于在芯片或多芯片封装的分层静态时序分析期间验证时钟偏移的方法和系统。 分层模块的每对时钟输入限制了可允许的时钟偏移，从而在传播到这些时钟输入的时钟输入到达时间上产生新的相对约束。 一个实施例基于确定的到达时间和在所述时钟输入处的计算的松弛值的最大值，而第二实施例基于确定的到达时间和最小的下游测试松弛值。 该方法还将模块时钟断言转换成一组相对时序约束，以便即使在模块分析时绝对定时到达不是完全知道的情况下也允许分层定时签发。

公开(公告)号：US20110077882A1

公开(公告)日：2011-03-31

申请号：US12568985

申请日：2009-09-29

申请人： Bhavna Agrawal ,  David J. Hathaway ,  Pravin P. Kamdar ,  Karl K. Moody, III ,  Peng Peng ,  David W. Winston

发明人： Bhavna Agrawal ,  David J. Hathaway ,  Pravin P. Kamdar ,  Karl K. Moody, III ,  Peng Peng ,  David W. Winston

IPC分类号： G06F19/00 ,  G01R27/00

CPC分类号： G06F17/5022

摘要： Disclosed are embodiments of a system and of an associated method for estimating the leakage current of an electronic circuit. The embodiments analyze a layout of an electronic circuit in order to identify all driven and non-driven nets within the electronic circuit, to identify all of the driven net-bounded partitions within the electronic circuit (based on the driven and non-driven nets), and to identify, for each driven net-bounded partition, all possible states of the electronic circuit that can leak. Then, using this information, the embodiments estimate the leakage current of the electronic circuit. This is accomplished by first determining, for each state of each driven net-bounded partition, a leakage current of the driven net-bounded partition and a probability that the state will occur in the driven net-bounded partition during operation of the electronic circuit. Then, for each state of each driven net-bounded partition, the leakage current of the driven net-bounded partition and the state probability are multiplied together. The results are then aggregated.

摘要翻译： 公开了用于估计电子电路的漏电流的系统和相关方法的实施例。 实施例分析电子电路的布局，以便识别电子电路内的所有被驱动和非驱动的网络，以识别电子电路内的所有被驱动的网络边界的分区（基于被驱动和非驱动的网络） 并且为每个被驱动的有界分区识别可能泄漏的电子电路的所有可能的状态。 然后，使用该信息，实施例估计电子电路的漏电流。 这是通过首先确定每个受驱动网络边界分区的每个状态，驱动网络边界分区的泄漏电流以及在电子电路运行期间状态将在驱动网络划分区域内发生的概率来实现的。 然后，对于每个被驱动的有界分区的每个状态，驱动的有界分区的泄漏电流和状态概率相乘。 然后汇总结果。

公开(公告)号：US07844933B2

公开(公告)日：2010-11-30

申请号：US12113288

申请日：2008-05-01

申请人： Joseph M. Frank ,  David J. Hathaway ,  Kerim Kalafala

发明人： Joseph M. Frank ,  David J. Hathaway ,  Kerim Kalafala

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method of optimizing timing of signals within an integrated circuit design using proxy slack values propagates signals through the integrated circuit design to output timing signals. For early mode timing analysis, the method sets an early proxy slack value to zero if the late slack value is less than zero. Otherwise, if the late slack value is not less than zero, the method restricts the early proxy slack value to a maximum of the early slack value and the negative of the late slack value. To the contrary, for late mode timing analysis, the method sets a late proxy slack value to zero if the early slack value is less than zero. Otherwise, if the early proxy slack value is not less than zero, the method restricts the late proxy slack value to a maximum of the late slack value and the negative of the early slack value.

摘要翻译： 使用代理松弛值在集成电路设计中优化信号定时的方法通过集成电路设计传播信号以输出定时信号。 对于早期模式时序分析，如果迟滞值小于零，则该方法将早期代理松弛值设置为零。 否则，如果迟到的值不小于零，则该方法将早期代理松弛值限制为早期松弛值的最大值和后期松弛值的负值。 相反，对于晚期模式时序分析，如果早期松弛值小于零，则该方法将较晚的代理松弛值设置为零。 否则，如果早期代理松弛值不小于零，则该方法将后期代理松弛值限制为最小的延迟松弛值，并将早期松弛值的负值限制。

公开(公告)号：US07793176B2

公开(公告)日：2010-09-07

申请号：US11696981

申请日：2007-04-05

申请人： Gary D. Grise ,  David J. Hathaway ,  Vikram Iyengar

发明人： Gary D. Grise ,  David J. Hathaway ,  Vikram Iyengar

IPC分类号： G01R31/28

CPC分类号： G01R31/31715 ,  G01R31/31707 ,  G01R31/318328

摘要： A method for automatically generating test patterns for digital logic circuitry using an automatic test pattern generation tool. The method includes generating test patterns and applying faulty behavior to various paths within the digital logic circuitry. As each circuit path is tested, tested circuit nodes along the circuit path are marked as “exercised.” Subsequent test paths are assembled by avoiding marked circuit nodes. In this manner, coverage of paths tested may be increased and many circuit nodes can be tested efficiently.

摘要翻译： 一种使用自动测试图案生成工具自动生成数字逻辑电路测试图案的方法。 该方法包括生成测试模式并将故障行为应用于数字逻辑电路内的各种路径。 随着每个电路路径的测试，沿着电路路径的测试电路节点被标记为“行使”。随后的测试路径通过避免标记的电路节点进行组装。 以这种方式，可以增加测试路径的覆盖范围，并且可以有效地测试许多电路节点。