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146 条记录 (耗时 0.04 秒)

    0th droop detector architecture and implementation
    62.
    发明授权
    0th droop detector architecture and implementation 有权
    第0个下垂检测器架构和实现

    公开(公告)号：US07528619B2

    公开(公告)日：2009-05-05

    申请号：US11172250

    申请日：2005-06-30

    申请人： Fabrice Paillet ,  Tanay Karnik ,  Jianping Xu ,  Vivek K. De

    发明人： Fabrice Paillet ,  Tanay Karnik ,  Jianping Xu ,  Vivek K. De

    IPC分类号： G01R31/00 ,  G01R19/00

    CPC分类号： H03K19/00346

    摘要： A voltage droop detector captures the very high-frequency noise on the power grid of a load, such as a microprocessor. The droop detector includes twin circuits, one of which receives the voltage from the power grid of the load, the other of which receives a filtered voltage. A 0th droop, as well as 1st droops, 2nd droops, and so on, are captured and stored for subsequent analysis. The circuits sample the voltages frequently enough to ensure that all droop events are captured. Other embodiments are described and claimed.

    摘要翻译： 电压下降检测器捕获诸如微处理器的负载的电网上的非常高频噪声。 下垂检测器包括双电路，其中一个接收来自负载的电网的电压，另一个接收经滤波的电压。 第0次下垂以及第1次下垂，第2次下垂等，被捕获并存储以供后续分析。 电路频繁地对电压进行采样，以确保捕获所有下垂事件。 描述和要求保护其他实施例。

    Low-swing level shifter
    63.
    发明授权
    Low-swing level shifter 有权
    低摆幅电平转换器

    公开(公告)号：US07215173B2

    公开(公告)日：2007-05-08

    申请号：US11047442

    申请日：2005-01-31

    申请人： Fabrice Paillet ,  David J. Rennie ,  Tanay Karnik ,  Jianping Xu

    发明人： Fabrice Paillet ,  David J. Rennie ,  Tanay Karnik ,  Jianping Xu

    IPC分类号： H03L5/00

    CPC分类号： H03K19/018507

    摘要： In general, in one aspect, the disclosure describes an apparatus for shifting a low swing signal. The apparatus includes a first pair of transistors to receive a first input signal and a second input signal and to generate a first output signal that is a shifted version of the first input signal. The apparatus further includes a second pair of transistors to receive the first input signal and the second input signal and to generate a second output signal that is a shifted version of the second input signal.

    摘要翻译： 通常，在一个方面，本公开描述了一种用于移动低挥杆信号的装置。 该装置包括第一对晶体管，用于接收第一输入信号和第二输入信号，并产生作为第一输入信号的偏移版本的第一输出信号。 该装置还包括第二对晶体管，用于接收第一输入信号和第二输入信号，并产生作为第二输入信号的移位版本的第二输出信号。

    Delay interpolation in a ring oscillator delay stage
    64.
    发明申请
    Delay interpolation in a ring oscillator delay stage 有权
    延迟内插在环形振荡器延迟阶段

    公开(公告)号：US20060071722A1

    公开(公告)日：2006-04-06

    申请号：US10953023

    申请日：2004-09-29

    申请人： Fabrice Paillet ,  David Rennie ,  Tanay Karnik ,  Jianping Xu

    发明人： Fabrice Paillet ,  David Rennie ,  Tanay Karnik ,  Jianping Xu

    IPC分类号： H03K3/03

    CPC分类号： H03K3/0322

    摘要： According to some embodiments, a circuit includes a delay stage of a ring oscillator. The delay stage may include a first differential pair, a second differential pair, and a third differential pair. The first differential pair may be coupled to a first current-steering circuit, receive a differential input signal, and output a first differential signal. The second differential pair may receive the differential input signal and output a second differential signal, and the third differential pair may be coupled to a second current-steering circuit, receive the second differential signal from the second differential pair, and output the first differential signal. An amount of delay between the differential input signal and the first differential signal is based on relative amounts of current steered by the first current-steering circuit and the second current-steering circuit.

    摘要翻译： 根据一些实施例，电路包括环形振荡器的延迟级。 延迟级可以包括第一差分对，第二差分对和第三差分对。 第一差分对可以耦合到第一电流转向电路，接收差分输入信号，并输出第一差分信号。 第二差分对可以接收差分输入信号并输出​​第二差分信号，并且第三差分对可以耦合到第二电流导向电路，从第二差分对接收第二差分信号，并输出第一差分信号 。 差分输入信号和第一差分信号之间的延迟量是基于由第一电流转向电路和第二电流转向电路转向的电流的相对量。

    Programmable high-resolution timing jitter injectors
    65.
    发明申请
    Programmable high-resolution timing jitter injectors 有权
    可编程高分辨率定时抖动注入器

    公开(公告)号：US20060061399A1

    公开(公告)日：2006-03-23

    申请号：US10946709

    申请日：2004-09-22

    申请人： Jianping Xu ,  KyeHyung Lee ,  Fabrice Paillet ,  David Rennie ,  Tanay Karnik

    发明人： Jianping Xu ,  KyeHyung Lee ,  Fabrice Paillet ,  David Rennie ,  Tanay Karnik

    IPC分类号： H03H11/26

    CPC分类号： H03K5/1504 ,  H03K5/133 ,  H03K2005/00058

    摘要： A device includes a first circuit having rows and columns of delay cells to generate delayed signals based on an input signal. The delayed signals are selectable and have a different delay from one another with respect to the input signal. The device is programmable based on a delay code. Different values of the delay code allow the device to select different delayed signals. The device may select one of the delayed signals from the first circuit for use as a timing signal in a second circuit of the device. The device may also use the delayed signals from the first circuit to evaluate a clock and data recovery circuit. In an embodiment, the circuits may be located on a single die.

    摘要翻译： 一种装置包括具有行和列的延迟单元的第一电路，以基于输入信号产生延迟信号。 延迟信号是可选择的并且相对于输入信号具有彼此不同的延迟。 该设备可以基于延迟码进行编程。 延迟码的不同值允许设备选择不同的延迟信号。 设备可以选择来自第一电路的延迟信号之一用作设备的第二电路中的定时信号。 该装置还可以使用来自第一电路的延迟信号来评估时钟和数据恢复电路。 在一个实施例中，电路可以位于单个管芯上。

    Interpolation delay cell for 2ps resolution jitter injector in optical link transceiver
    68.
    发明申请
    Interpolation delay cell for 2ps resolution jitter injector in optical link transceiver 失效
    用于光链路收发器中2ps分辨率抖动注入器的插值延迟单元

    公开(公告)号：US20050140412A1

    公开(公告)日：2005-06-30

    申请号：US10748300

    申请日：2003-12-31

    申请人： KyeHyung Lee ,  Jianping Xu ,  Fabrice Paillet ,  Tanay Karnik

    发明人： KyeHyung Lee ,  Jianping Xu ,  Fabrice Paillet ,  Tanay Karnik

    IPC分类号： H03F1/26 ,  H03F3/45 ,  H03H11/26

    CPC分类号： H03H11/265 ,  H03F1/26 ,  H03F3/45183 ,  H03F3/45475 ,  H03F2200/372

    摘要： An apparatus and method for generating signals with improved timing resolution includes a delay cell configured to receive dual coupled differential input signals. The delay cell performs an interpolation function which smooths state transitions or other discontinuities that result from timing or phase offsets between the input signals. The interpolation function is performed by resistors which couple respective components of the differential inputs prior to traversing delay paths. A delay cell of this type has high supply noise rejection and a low output swing range, thereby making it suitable for a number of applications. One application includes a jitter noise generator which uses the delay cell to achieve improved timing resolution and which is not limited by a minimum delay of the cell. Another application uses the delay cell to form a coupled delay line.

    摘要翻译： 用于产生具有改进的定时分辨率的信号的装置和方法包括被配置为接收双耦合差分输入信号的延迟单元。 延迟单元执行内插函数，其平滑由输入信号之间的定时或相位偏移导致的状态转换或其他不连续性。 内插函数由在穿过延迟路径之前耦合差分输入的各个分量的电阻器来执行。 这种延迟单元具有高的电源噪声抑制和低的输出摆​​幅范围，从而使其适用于多种应用。 一个应用包括抖动噪声发生器，其使用延迟单元来实现改进的定时分辨率，并且不受单元的最小延迟的限制。 另一应用使用延迟单元来形成耦合的延迟线。

    Laser driver for high speed short distance links
    69.
    发明授权
    Laser driver for high speed short distance links 有权
    用于高速短距离连接的激光驱动器

    公开(公告)号：US07505497B2

    公开(公告)日：2009-03-17

    申请号：US10816321

    申请日：2004-03-31

    申请人： Jianping Xu ,  Fabrice Paillet ,  Tanay Karnik

    发明人： Jianping Xu ,  Fabrice Paillet ,  Tanay Karnik

    IPC分类号： H01S3/00

    CPC分类号： H04B10/564 ,  H01S5/0427 ,  H01S5/183 ,  H04B10/503

    摘要： One embodiment of a laser driver for high speed interconnections includes a buffered level shifter to shift the input voltage level to an appropriate level. In some embodiments the buffered level shifter may be tuned to provide a desired level shift with impedance matched to the driving load. Another embodiment converts a digital signal to a current train of a bias mode to represent logical zero and of a modulation mode to represent logical one, wherein one or both of the bias mode and modulation mode may be adjusted, for example by a programmable control circuit or by an adaptive control circuit. Some embodiments also provide circuitry for reducing overshoot of the output signal.

    摘要翻译： 用于高速互连的激光驱动器的一个实施例包括用于将输入电压电平转换到适当电平的缓冲电平移位器。 在一些实施例中，缓冲电平移位器可以被调谐以提供具有与驱动负载匹配的阻抗的期望电平移位。 另一个实施例将数字信号转换为偏置模式的当前列，以表示逻辑零和调制模式以表示逻辑1，其中偏置模式和调制模式中的一个或两个可以例如由可编程控制电路 或通过自适应控制电路。 一些实施例还提供用于减少输出信号的过冲的电路。

    Programmable high-resolution timing jitter injectors high-resolution timing jitter injectors
    70.
    发明授权
    Programmable high-resolution timing jitter injectors high-resolution timing jitter injectors 有权
    可编程高分辨率定时抖动注入器高分辨率定时抖动注入器

    公开(公告)号：US07348821B2

    公开(公告)日：2008-03-25

    申请号：US10946709

    申请日：2004-09-22

    申请人： Jianping Xu ,  KyeHyung Lee ,  Fabrice Paillet ,  David Rennie ,  Tanay Karnik

    发明人： Jianping Xu ,  KyeHyung Lee ,  Fabrice Paillet ,  David Rennie ,  Tanay Karnik

    IPC分类号： H03H11/26

    CPC分类号： H03K5/1504 ,  H03K5/133 ,  H03K2005/00058

    摘要： A device includes a first circuit having rows and columns of delay cells to generate delayed signals based on an input signal. The delayed signals are selectable and have a different delay from one another with respect to the input signal. The device is programmable based on a delay code. Different values of the delay code allow the device to select different delayed signals. The device may select one of the delayed signals from the first circuit for use as a timing signal in a second circuit of the device. The device may also use the delayed signals from the first circuit to evaluate a clock and data recovery circuit. In an embodiment, the circuits may be located on a single die.

    摘要翻译： 一种装置包括具有行和列的延迟单元的第一电路，以基于输入信号产生延迟信号。 延迟信号是可选择的并且相对于输入信号具有彼此不同的延迟。 该设备可以基于延迟码进行编程。 延迟码的不同值允许设备选择不同的延迟信号。 设备可以选择来自第一电路的延迟信号之一用作设备的第二电路中的定时信号。 该装置还可以使用来自第一电路的延迟信号来评估时钟和数据恢复电路。 在一个实施例中，电路可以位于单个管芯上。