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    Sense-amplification with offset cancellation for static random access memories
    1.
    发明授权
    Sense-amplification with offset cancellation for static random access memories 有权
    用于静态随机存取存储器的偏移消除的感测放大

    公开(公告)号：US08488403B2

    公开(公告)日：2013-07-16

    申请号：US12757033

    申请日：2010-04-08

    申请人： Manoj Sachdev ,  Mohammad Sharifkhani ,  Jaspal Singh Shah ,  David Rennie

    发明人： Manoj Sachdev ,  Mohammad Sharifkhani ,  Jaspal Singh Shah ,  David Rennie

    IPC分类号： G11C7/02

    CPC分类号： G11C7/062 ,  G11C2207/063 ,  G11C2207/104

    摘要： An offset cancellation scheme for sense amplification is described. The scheme consists of group of transistors which are selectively coupled to high and low voltage levels via multi-phase timing. This results in a voltage level on sensing nodes of interest which are a function of transistor mismatch. The resulting voltage levels act to compensates for the transistor mismatch, thereby improving the reliability of the sense amplifier in the presence of process non-idealities. The offset cancellation scheme is applicable to numerous types of sense amplifiers, amplifiers, and comparators.

    摘要翻译： 描述了用于感测放大的偏移消除方案。 该方案由通过多相定时选择性地耦合到高电压和低电压电平的晶体管组成。 这导致感兴趣的感测节点上的电压电平，其是晶体管不匹配的函数。 所产生的电压电平用于补偿晶体管失配，从而在存在工艺非理想性的情况下提高读出放大器的可靠性。 偏移消除方案适用于许多类型的读出放大器，放大器和比较器。

    SRAM cell without dedicated access transistors
    2.
    发明授权
    SRAM cell without dedicated access transistors 有权
    没有专用存取晶体管的SRAM单元

    公开(公告)号：US08072797B2

    公开(公告)日：2011-12-06

    申请号：US12494908

    申请日：2009-06-30

    申请人： Manoj Sachdev ,  David Rennie

    发明人： Manoj Sachdev ,  David Rennie

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412

    摘要： A Static Random Access Memory (SRAM) cell without dedicated access transistors is described. The SRAM cell comprises a plurality of transistors configured to provide at least a pair of storage nodes for storing complementary logic values represented by corresponding voltages. The transistors comprise at least one bitline transistor, at least on wordline transistor and at least two supply transistors. The bitline transistor is configured to selectively couple one of the storage nodes to at least one corresponding bitline, the bitline for being shared by SRAM cells in one of a common row or column. The wordline transistor is configured to selectively couple another of the storage nodes to at least one corresponding wordline, the wordline for being shared by SRAM cells in the other of the common row or column. The supply transistors are configured to selectively couple corresponding ones of the storage nodes to a supply voltage.

    摘要翻译： 描述了没有专用存取晶体管的静态随机存取存储器（SRAM）单元。 SRAM单元包括多个晶体管，其被配置为提供至少一对存储节点，用于存储由对应电压表示的互补逻辑值。 晶体管至少在字线晶体管和至少两个电源晶体管上包括至少一个位线晶体管。 位线晶体管被配置为选择性地将存储节点之一耦合到至少一个相应的位线，该位线用于由公共行或列之一中的SRAM单元共享的位线。 字线晶体管被配置为选择性地将另一个存储节点耦合到至少一个相应的字线，该字线由公共行或列中的另一个中的SRAM单元共享。 电源晶体管被配置为选择性地将相应的存储节点耦合到电源电压。

    Delay interpolation in a ring oscillator delay stage
    4.
    发明申请
    Delay interpolation in a ring oscillator delay stage 有权
    延迟内插在环形振荡器延迟阶段

    公开(公告)号：US20060071722A1

    公开(公告)日：2006-04-06

    申请号：US10953023

    申请日：2004-09-29

    申请人： Fabrice Paillet ,  David Rennie ,  Tanay Karnik ,  Jianping Xu

    发明人： Fabrice Paillet ,  David Rennie ,  Tanay Karnik ,  Jianping Xu

    IPC分类号： H03K3/03

    CPC分类号： H03K3/0322

    摘要： According to some embodiments, a circuit includes a delay stage of a ring oscillator. The delay stage may include a first differential pair, a second differential pair, and a third differential pair. The first differential pair may be coupled to a first current-steering circuit, receive a differential input signal, and output a first differential signal. The second differential pair may receive the differential input signal and output a second differential signal, and the third differential pair may be coupled to a second current-steering circuit, receive the second differential signal from the second differential pair, and output the first differential signal. An amount of delay between the differential input signal and the first differential signal is based on relative amounts of current steered by the first current-steering circuit and the second current-steering circuit.

    摘要翻译： 根据一些实施例，电路包括环形振荡器的延迟级。 延迟级可以包括第一差分对，第二差分对和第三差分对。 第一差分对可以耦合到第一电流转向电路，接收差分输入信号，并输出第一差分信号。 第二差分对可以接收差分输入信号并输出​​第二差分信号，并且第三差分对可以耦合到第二电流导向电路，从第二差分对接收第二差分信号，并输出第一差分信号 。 差分输入信号和第一差分信号之间的延迟量是基于由第一电流转向电路和第二电流转向电路转向的电流的相对量。

    Programmable high-resolution timing jitter injectors
    5.
    发明申请
    Programmable high-resolution timing jitter injectors 有权
    可编程高分辨率定时抖动注入器

    公开(公告)号：US20060061399A1

    公开(公告)日：2006-03-23

    申请号：US10946709

    申请日：2004-09-22

    申请人： Jianping Xu ,  KyeHyung Lee ,  Fabrice Paillet ,  David Rennie ,  Tanay Karnik

    发明人： Jianping Xu ,  KyeHyung Lee ,  Fabrice Paillet ,  David Rennie ,  Tanay Karnik

    IPC分类号： H03H11/26

    CPC分类号： H03K5/1504 ,  H03K5/133 ,  H03K2005/00058

    摘要： A device includes a first circuit having rows and columns of delay cells to generate delayed signals based on an input signal. The delayed signals are selectable and have a different delay from one another with respect to the input signal. The device is programmable based on a delay code. Different values of the delay code allow the device to select different delayed signals. The device may select one of the delayed signals from the first circuit for use as a timing signal in a second circuit of the device. The device may also use the delayed signals from the first circuit to evaluate a clock and data recovery circuit. In an embodiment, the circuits may be located on a single die.

    摘要翻译： 一种装置包括具有行和列的延迟单元的第一电路，以基于输入信号产生延迟信号。 延迟信号是可选择的并且相对于输入信号具有彼此不同的延迟。 该设备可以基于延迟码进行编程。 延迟码的不同值允许设备选择不同的延迟信号。 设备可以选择来自第一电路的延迟信号之一用作设备的第二电路中的定时信号。 该装置还可以使用来自第一电路的延迟信号来评估时钟和数据恢复电路。 在一个实施例中，电路可以位于单个管芯上。

    Sense-Amplification With Offset Cancellation For Static Random Access Memories
    7.
    发明申请
    Sense-Amplification With Offset Cancellation For Static Random Access Memories 有权
    用于静态随机存取存储器的偏移消除的感测放大

    公开(公告)号：US20110255359A1

    公开(公告)日：2011-10-20

    申请号：US12757033

    申请日：2010-04-08

    申请人： Manoj Sachdev ,  Mohammad Sharifkhani ,  Jaspal Singh Shah ,  David Rennie

    发明人： Manoj Sachdev ,  Mohammad Sharifkhani ,  Jaspal Singh Shah ,  David Rennie

    IPC分类号： G11C7/06 ,  H03F3/16

    CPC分类号： G11C7/062 ,  G11C2207/063 ,  G11C2207/104

    摘要： An offset cancellation scheme for sense amplification is described. The scheme consists of group of transistors which are selectively coupled to high and low voltage levels via multi-phase timing. This results in a voltage level on nodes of interest which are a function of transistor mismatch. The resulting voltage levels act to compensates for the transistor mismatch, thereby improving the reliability of the sense amplifier in the presence of process non-idealities. The offset cancellation scheme is applicable to numerous types of sense amplifiers.

    摘要翻译： 描述了用于感测放大的偏移消除方案。 该方案由通过多相定时选择性地耦合到高电压和低电压电平的晶体管组成。 这导致感兴趣的节点上的电压电平是晶体管不匹配的函数。 所产生的电压电平用于补偿晶体管失配，从而在存在工艺非理想性的情况下提高读出放大器的可靠性。 偏移消除方案适用于多种类型的读出放大器。

    SRAM CELL WITHOUT DEDICATED ACCESS TRANSISTORS
    8.
    发明申请
    SRAM CELL WITHOUT DEDICATED ACCESS TRANSISTORS 有权
    没有专用访问晶体管的SRAM单元

    公开(公告)号：US20100110773A1

    公开(公告)日：2010-05-06

    申请号：US12494908

    申请日：2009-06-30

    申请人： Manoj Sachdev ,  David Rennie

    发明人： Manoj Sachdev ,  David Rennie

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G11C11/412

    摘要： A Static Random Access Memory (SRAM) cell without dedicated access transistors is described. The SRAM cell comprises a plurality of transistors configured to provide at least a pair of storage nodes for storing complementary logic values represented by corresponding voltages. The transistors comprise at least one bitline transistor, at least on wordline transistor and at least two supply transistors. The bitline transistor is configured to selectively couple one of the storage nodes to at least one corresponding bitline, the bitline for being shared by SRAM cells in one of a common row or column. The wordline transistor is configured to selectively couple another of the storage nodes to at least one corresponding wordline, the wordline for being shared by SRAM cells in the other of the common row or column. The supply transistors are configured to selectively couple corresponding ones of the storage nodes to a supply voltage.

    摘要翻译： 描述了没有专用存取晶体管的静态随机存取存储器（SRAM）单元。 SRAM单元包括多个晶体管，其被配置为提供至少一对存储节点，用于存储由对应电压表示的互补逻辑值。 晶体管至少在字线晶体管和至少两个电源晶体管上包括至少一个位线晶体管。 位线晶体管被配置为选择性地将存储节点之一耦合到至少一个相应的位线，该位线用于由公共行或列之一中的SRAM单元共享的位线。 字线晶体管被配置为选择性地将另一个存储节点耦合到至少一个相应的字线，该字线由公共行或列中的另一个中的SRAM单元共享。 电源晶体管被配置为选择性地将相应的存储节点耦合到电源电压。

    Delay interpolation in a ring oscillator delay stage
    9.
    发明授权
    Delay interpolation in a ring oscillator delay stage 有权

    公开(公告)号：US07088191B2

    公开(公告)日：2006-08-08

    申请号：US10953023

    申请日：2004-09-29

    申请人： Fabrice Paillet ,  David Rennie ,  Tanay Karnik ,  Jianping Xu

    发明人： Fabrice Paillet ,  David Rennie ,  Tanay Karnik ,  Jianping Xu

    IPC分类号： H03K3/03 ,  H03L7/00

    CPC分类号： H03K3/0322

    摘要： According to some embodiments, a circuit includes a delay stage of a ring oscillator. The delay stage may include a first differential pair, a second differential pair, and a third differential pair. The first differential pair may be coupled to a first current-steering circuit, receive a differential input signal, and output a first differential signal. The second differential pair may receive the differential input signal and output a second differential signal, and the third differential pair may be coupled to a second current-steering circuit, receive the second differential signal from the second differential pair, and output the first differential signal. An amount of delay between the differential input signal and the first differential signal is based on relative amounts of current steered by the first current-steering circuit and the second current-steering circuit.

    Low-swing level shifter
    10.
    发明申请
    Low-swing level shifter 有权
    低摆幅电平转换器

    公开(公告)号：US20060170481A1

    公开(公告)日：2006-08-03

    申请号：US11047442

    申请日：2005-01-31

    申请人： Fabrice Paillet ,  David Rennie ,  Tanay Karnik ,  Jianping Xu

    发明人： Fabrice Paillet ,  David Rennie ,  Tanay Karnik ,  Jianping Xu

    IPC分类号： H03B1/00

    CPC分类号： H03K19/018507

    摘要： In general, in one aspect, the disclosure describes an apparatus for shifting a low swing signal. The apparatus includes a first pair of transistors to receive a first input signal and a second input signal and to generate a first output signal that is a shifted version of the first input signal. The apparatus further includes a second pair of transistors to receive the first input signal and the second input signal and to generate a second output signal that is a shifted version of the second input signal.

    摘要翻译： 通常，在一个方面，本公开描述了一种用于移动低挥杆信号的装置。 该装置包括第一对晶体管，用于接收第一输入信号和第二输入信号，并产生作为第一输入信号的偏移版本的第一输出信号。 该装置还包括第二对晶体管，用于接收第一输入信号和第二输入信号，并产生作为第二输入信号的移位版本的第二输出信号。