公开(公告)号：US20160013958A1

公开(公告)日：2016-01-14

申请号：US14328556

申请日：2014-07-10

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Timothy Mowry Hollis

IPC: H04L25/49 ,  H04L25/06 ,  H04L27/06

CPC classification number: H04L25/4927 ,  H04L25/0292 ,  H04L25/0298 ,  H04L25/06 ,  H04L25/4915 ,  H04L25/4917 ,  H04L27/06

Abstract: High-speed data links between a processor and off-chip DRAM utilizes pulse-amplitude-modulation (PAM) signaling to increase data rate for a given bandwidth and resource budget in SoCs. However, the termination resistor used in the transmission line interface between processor and DRAM consumes large amounts of power during PAM signaling. By adding a biasing source between Ground and the termination resistor, the “floor voltage” that the termination resistor uses as a reference for determining signaling levels may be raised. Raising the floor voltage reduces the amount of voltage across the termination resistor and reduces power consumption accordingly. The biasing source is adjusted to various increments of the maximum amplitude of the PAM signaling. A floor voltage of one-half of the maximum amplitude of PAM signaling produces minimum power consumption in the receiver. Additionally, data inversion pre-coding may be concatenated with the floor voltage adjustment to further maximize power savings of the interface.

Abstract translation: 处理器和片外DRAM之间的高速数据链路利用脉冲幅度调制（PAM）信号来提高SoC中给定带宽和资源预算的数据速率。 然而，处理器和DRAM之间的传输线接口中使用的终端电阻在PAM信令期间消耗大量的功率。 通过在接地端子和终端电阻之间增加一个偏压源，终端电阻器用作确定信号电平的基准的“底电压”可能会提高。 提高地板电压会降低终端电阻两端的电压，从而降低功耗。 偏置源被调整到PAM信号的最大幅度的各种增量。 PAM信令的最大幅度的一半的地电压在接收机中产生最小功耗。 另外，数据反转预编码可以与底层电压调整相连接，以进一步最大化接口的功率节省。

公开(公告)号：US11907149B2

公开(公告)日：2024-02-20

申请号：US17116454

申请日：2020-12-09

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Yiftach Benjamini

IPC: G06F13/38 ,  G06F13/42

CPC classification number: G06F13/385 ,  G06F13/4213 ,  G06F13/4226 ,  G06F2213/0042

Abstract: Sideband signaling in Universal Serial Bus (USB) Type-C communication link allows multiple protocols that are tunneled through a USB link, where sideband signals may be provided through the sideband use (SBU) pins. Further, the SBU pins may be transitioned between different modes of sideband signals. In particular, signals in an initial mode may indicate a need or desire transition to a second mode. After a negotiation, linked devices agree to transition, the two devices may transition to the second mode. By providing this inband sideband signaling that allows mode changes, more protocols can be tunneled with accompanying sideband signaling and flexibility of the USB link is expanded.

公开(公告)号：US11886366B2

公开(公告)日：2024-01-30

申请号：US17677731

申请日：2022-02-22

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Umesh Srikantiah ,  Richard Dominic Wietfeldt

IPC: G06F13/362 ,  G06F1/12 ,  G06F13/42 ,  H04L12/40

CPC classification number: G06F13/362 ,  G06F1/12 ,  G06F13/4282 ,  H04L12/40

Abstract: An apparatus coupled to a single-wire serial bus through a line driver is configured to determine that a first sequence start condition (SSC) has been initiated when the single-wire serial bus transitions from first to second signaling states. The line driver drives the single-wire serial bus to the first signaling state after a first duration to complete the first SSC, and an arbitration window with plural timeslots is provided when the line driver presents a high impedance to the single-wire serial bus after the first SSC. The line driver drives the single-wire serial bus to the first signaling state in each timeslot of the plural timeslots in which the single-wire serial bus is driven to the second signaling state. After the arbitration window has expired, the apparatus transmits a second SSC and a Manchester encoded command addressed to at least one slave device.

公开(公告)号：US11520727B2

公开(公告)日：2022-12-06

申请号：US16952229

申请日：2020-11-19

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Mohit Kishore Prasad ,  Richard Dominic Wietfeldt ,  James Lionel Panian

IPC: G06F13/42

Abstract: Alternate sideband signaling in a Peripheral Component Interconnect (PCI) express (PCIE) link may be enabled over existing sideband lines in a conventional PCIE link. For example, the default sideband communication of PCIE may be changed to a Universal Asynchronous receiver/transmitter (UART), line multiplex UART (LM-UART), serial peripheral interface (SPI), I2C, or I3C mode of communication. This change may be negotiated between the host and slave of the communication link, with a transition occurring after the negotiation concludes. The new mode of communication may include or encode the conventional PCIE sideband signals.

公开(公告)号：US11513991B2

公开(公告)日：2022-11-29

申请号：US17061357

申请日：2020-10-01

Applicant: QUALCOMM Incorporated

Inventor： Richard Dominic Wietfeldt ,  Lalan Jee Mishra ,  Radu Pitigoi-Aron

IPC: G06F13/42

Abstract: Systems, methods, and apparatus for communication virtualized general-purpose input/output (GPIO) signals and control messages over a serial communication link. An apparatus includes a serial bus, and a controller configured to represent a series of signaling state of physical general-purpose input/output (GPIO) in a batch that comprises a sequence of virtual GPIO messages and control messages, generate a first header that includes timing information configured to control timing of execution of the batch, transmit the first header over a communication link, and transmit the batch over the communication link.

公开(公告)号：US20220200650A1

公开(公告)日：2022-06-23

申请号：US17127709

申请日：2020-12-18

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Umesh Srikantiah ,  Karthik Manivannan

IPC: H04B1/401 ,  G06F13/40 ,  G06F13/42

Abstract: Systems and methods for variable stride counting for timed-triggers in a radio frequency front end (RFFE) bus modify how a master clock controls counters in slaves. In particular, instead of having the master clock change a counter at a slave device on a one-to-one clock tick-to-counter change, exemplary aspects of the present disclosure contemplate allowing a bus ownership master (BOM) to select a stride size wherein each clock tick causes the counter to change by the size of the stride. Clock ticks are then sent less frequently over the clock line of the RFFE bus. In this fashion, fewer clock ticks are required to change the counter to the trigger event.

公开(公告)号：US11177856B2

公开(公告)日：2021-11-16

申请号：US16780509

申请日：2020-02-03

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Soon-Seng Lau

IPC: H04W4/00 ,  H04B3/487 ,  H04B3/06 ,  H04L27/00

Abstract: Crosstalk amelioration systems and methods in a radio frequency front end (RFFE) communication system provide a host or master of an RFFE bus to monitor a weakly-driven data line in the RFFE bus while a clock line is actively providing a clock signal for trigger events at one or more slaves on the RFFE bus. If the host detects noise on the data line that looks like a sequence start condition (SSC) signal, the host further signals on the data line to negate the impact of the false SSC signal and thus avoid misinterpretation by the slaves.

公开(公告)号：US10983552B2

公开(公告)日：2021-04-20

申请号：US16507904

申请日：2019-07-10

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt

IPC: G06F1/10 ,  G06F13/42 ,  G06F13/362

Abstract: Systems, methods, and apparatus for improving bus latency are described. Clock-cycle overhead associated with the transmission of trigger activation information may be reduced through the use of optimized datagram structures for register-configurable trigger activation mechanisms. A first mechanism defines a command code with a first Trigger-Activation datagram, and a second mechanism defines a command code with a second Trigger-Activation datagram that uses a 4-bit Magic-ID and eliminates 18 clock cycles from the conventional Extended Register Write datagram structure. A method performed at a device coupled to a serial bus includes generating a datagram that does not have an address field, populating a data payload of the datagram with trigger activation information directed to a plurality of slave devices coupled to a serial bus, and transmitting the datagram over the serial bus. Transmission of the datagram serves as a trigger that causes a configuration change in at least one slave device.

公开(公告)号：US10963035B2

公开(公告)日：2021-03-30

申请号：US16155824

申请日：2018-10-09

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  James Lionel Panian ,  Richard Dominic Wietfeldt ,  Mohit Kishore Prasad ,  Amit Gil ,  Shaul Yohai Yifrach

IPC: G06F1/3234 ,  G06F13/40 ,  G06F13/10 ,  G06F1/3206

Abstract: A system for low-speed Peripheral Component Interconnect (PCI) Express (PCIe) systems, while maintaining both lower level physical layer (PHY) pin requirements and upper layer functionality being capable of both differential and single-ended signaling modes optimized for power savings. An apparatus includes an integrated circuit (IC) adapted to be connected to a Peripheral Component Interconnect (PCI) Express (PCIe) bus. The IC includes a control block selects between differential and single-ended signaling for the PCIe bus. The single-ended signaling is transmitted through existing pins of the IC that are coupled to the PCIe bus for differential signaling when single-ended signaling is selected for the PCIe bus.

公开(公告)号：US10693674B2

公开(公告)日：2020-06-23

申请号：US15882494

申请日：2018-01-29

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Radu Pitigoi-Aron

IPC: H04L12/40 ,  G06F13/42 ,  H04L25/49 ,  H04L1/16

Abstract: Systems, methods, and apparatus are described that enable a device to indicate availability of priority data to be communicated over a half-duplex serial bus without waiting for an ongoing transmission to be completed. In-datagram critical signaling is accommodated without breaking backward compatibility. A method implemented at a transmitting device coupled to a serial bus includes transmitting a data byte over a first line of the serial bus to a receiving device in accordance with a clock signal transmitted by a master device on a second line of the serial device, detecting a first pulse on the first line of the serial bus during a cycle of the clock signal designated for an acknowledgement or negative acknowledgement by the second device, and processing an alert indicated by the first pulse.