公开(公告)号：US20120110521A1

公开(公告)日：2012-05-03

申请号：US12915923

申请日：2010-10-29

申请人： Kanak B. Agarwal ,  Lars W. Liebmann ,  Sani R. Nassif

发明人： Kanak B. Agarwal ,  Lars W. Liebmann ,  Sani R. Nassif

IPC分类号： G06F17/50

CPC分类号： G03F1/70 ,  H01L27/0207

摘要： A mechanism is provided for converting a set of single-layer design rules into a set of split-layer design rules for double patterning lithography (DPL). The set of single-layer design rules and minimum lithographic resolution pitch constraints for single exposure are identified. The set of single-layer design rules comprise a first plurality of minimum distances that are required by a set of first shapes in a single-layer design. Each of the first plurality of minimum distances in the set of single-layer design rules are modified with regard to the minimum lithographic resolution pitch constraints for single exposure, thereby forming the set of split-layer design rules. The set of split-layer design rules comprise a second plurality of minimum distances that are required by a set of second shapes and a set of third shapes in a split-layer design. The set of split-layer design rules are then coded into a design rule checker.

摘要翻译： 提供了一种用于将一组单层设计规则转换为用于双重图案化光刻（DPL）的一组分裂层设计规则的机制。 确定了一套单层设计规则和单次曝光的最小光刻分辨率间距约束。 单层设计规则的集合包括单层设计中的一组第一形状所需的第一多个最小距离。 关于单次曝光的最小光刻分辨率间距约束修改单层设计规则集合中的第一多个最小距离中的每一个，从而形成分裂层设计规则集合。 分裂层设计规则的集合包括一组第二形状所需的第二多个最小距离和分裂层设计中的一组第三形状。 然后将该组分裂设计规则编码为设计规则检查器。

公开(公告)号：US08121822B2

公开(公告)日：2012-02-21

申请号：US12420891

申请日：2009-04-09

申请人： Emrah Acar ,  Kanak B. Agarwal ,  Damir Jamsek ,  Sani R. Nassif

发明人： Emrah Acar ,  Kanak B. Agarwal ,  Damir Jamsek ,  Sani R. Nassif

IPC分类号： G06F17/50 ,  G06F3/00

CPC分类号： G06F17/5036

摘要： In accordance with one embodiment, a plurality of empirical measurements of a fabricated integrated circuit including a fabricated transistor having multiple terminals is received. The plurality of empirical measurements each include an empirical terminal current set and an empirical terminal voltage set for the terminals of the fabricated transistor. A mathematical simulation model of a simulated transistor is also received. Utilizing the mathematical simulation model, an intermediate data set is calculated by determining, for each of a plurality of different terminal voltage sets, a simulated terminal current set and a simulated terminal charge set. A modeling tool processes the intermediate data set to obtain a time domain simulation model of the fabricated transistor that, for each of the plurality of empirical measurements, provides a simulated terminal charge set. The time domain simulation model is stored in a computer-readable data storage medium.

摘要翻译： 根据一个实施例，接收包括具有多个端子的制造晶体管的制造的集成电路的多个经验测量。 多个经验测量每个包括经验终端电流集合和为制造的晶体管的端子设置的经验终端电压。 还接收了模拟晶体管的数学模拟模型。 利用数学模拟模型，通过针对多个不同终端电压组中的每一个确定模拟终端电流集合和模拟终端电荷组来计算中间数据集。 建模工具处理中间数据集以获得制造的晶体管的时域仿真模型，对于多个经验测量中的每一个提供模拟终端电荷组。 时域仿真模型存储在计算机可读数据存储介质中。

公开(公告)号：US20110154271A1

公开(公告)日：2011-06-23

申请号：US12640166

申请日：2009-12-17

申请人： Kanak B. Agarwal ,  Sani R. Nassif

发明人： Kanak B. Agarwal ,  Sani R. Nassif

IPC分类号： G06F17/50

CPC分类号： G03F1/144 ,  G03F1/36

摘要： A method, computer program product, and data processing system for performing an improved optical proximity correction are disclosed, which better respect the electrical properties of the device being manufactured. A preferred embodiment of the present invention performs OPC by first dividing the perimeter of a mask region into a plurality of segments, then grouping the segments into at least two distinct groups, wherein segments in the first of these groups are adjusted in position so as to minimize edge placement error (EPE) when the photolithography using the mask is simulated. Segments in the second group are adjusted in position so as to minimize cumulative error in a dimension spanning the region, wherein the span of such dimension extends from segments in the first group to segments in the second group. Correction so obtained by this process more readily preserves the intended electrical behavior of the original device design.

摘要翻译： 公开了一种用于执行改进的光学邻近校正的方法，计算机程序产品和数据处理系统，其更好地尊重正在制造的设备的电气特性。 本发明的优选实施例通过首先将掩模区域的周边划分成多个段来执行OPC，然后将段分组成至少两个不同的组，其中这些组中的第一组中的段被调整到适当位置，以便 当模拟使用掩模的光刻时，最小化边缘放置误差（EPE）。 第二组中的段被调整位置，以便最小化横跨该区域的维度的累积误差，其中这种维度的跨度从第一组中的段延伸到第二组中的段。 通过该方法获得的校正更容易地保持原始设备设计的预期电气行为。

公开(公告)号：US20100262413A1

公开(公告)日：2010-10-14

申请号：US12420910

申请日：2009-04-09

申请人： Emrah Acar ,  Kanak B. Agarwal ,  Damir Jamsek ,  Sani R. Nassif

发明人： Emrah Acar ,  Kanak B. Agarwal ,  Damir Jamsek ,  Sani R. Nassif

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： According to a method of simulation data processing, a difference is determined between a simulated value of a characteristic for a simulated integrated circuit device and a corresponding empirical value of the characteristic for a fabricated integrated circuit device. A data structure containing a simulation model of the fabricated integrated circuit device is accessed, where the data structure includes a plurality of entries each accessed via a unique index and an index used to access the data structure is offset in accordance with the difference between the simulated value and the empirical value. Operation of the simulated integrated circuit device is then simulated utilizing a value obtained from one of the plurality of entries of the data structure. Results of the simulation are stored in a data storage medium.

摘要翻译： 根据模拟数据处理的方法，在仿真集成电路器件的特性的模拟值与制造的集成电路器件的特性的对应经验值之间确定差异。 访问包含制造的集成电路器件的仿真模型的数据结构，其中数据结构包括通过唯一索引访问的多个条目，并且用于访问数据结构的索引根据模拟的 价值和经验价值。 然后使用从数据结构的多个条目之一获得的值来模拟仿真集成电路器件的操作。 模拟结果存储在数据存储介质中。

公开(公告)号：US20100257493A1

公开(公告)日：2010-10-07

申请号：US12416222

申请日：2009-04-01

申请人： Kanak B. Agarwal ,  Vivek Joshi

发明人： Kanak B. Agarwal ,  Vivek Joshi

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： Disclosed is a computer implemented method and computer program product to determine metal oxide semiconductor (MOS) gate functional limitations. A simulator obtains a plurality of slices of a MOS gate, the slices each comprising at least one parameter, the parameter comprising a slice gate width and a slice gate length. The simulator determines a current for each slice based on a slice gate length of the slice to form a length-based current for each slice. The simulator determines a length-based current for the MOS gate by summing the length-based current for each slice. The simulator calculates a stress profile for each slice. The simulator determines a slice carrier mobility for each slice based on the stress profile of each slice. The simulator determines a carrier mobility-based current for each slice, based on each slice carrier mobility. The simulator determines a carrier mobility for the MOS gate based on the carrier mobility-based current for each slice. The simulator determines an effective length for the MOS gate based on the length-based current.

摘要翻译： 公开了一种用于确定金属氧化物半导体（MOS）门功能限制的计算机实现方法和计算机程序产品。 模拟器获得MOS门的多个片，每个片包括至少一个参数，该参数包括片栅宽度和片栅长度。 模拟器基于切片的切片门限长度确定每个切片的电流，以形成每个切片的基于长度的电流。 模拟器通过对每个切片的基于长度的电流求和来确定MOS栅极的基于长度的电流。 模拟器计算每个切片的应力分布。 模拟器基于每个切片的应力分布来确定每个切片的切片载波移动性。 模拟器基于每个切片载波移动性确定每个切片的基于载波移动性的电流。 模拟器基于每个切片的基于载波移动性的电流来确定MOS栅极的载流子迁移率。 模拟器基于长度电流确定MOS栅极的有效长度。

公开(公告)号：US07698079B2

公开(公告)日：2010-04-13

申请号：US11946571

申请日：2007-11-28

申请人： Dhruva J. Acharyya ,  Kanak B. Agarwal

发明人： Dhruva J. Acharyya ,  Kanak B. Agarwal

IPC分类号： G01R19/00

CPC分类号： G01R31/31718 ,  G01R31/3008

摘要： Measurement of individual quiescent supply currents from multiple power supply pads located across a semiconductor die provides a means of characterizing across-die variation. A ratio is created by combining the individual pad supply current with the sum of all pad supply currents for a given die. An n-tuple is formed from the set of ratios for all pad supply currents to provide a unique signature for different across-die variation profiles.

摘要翻译： 跨越半导体管芯的多个电源焊盘测量单个静态电源提供了一种表征跨裸片变化的方法。 通过将各个焊盘供应电流与给定裸片的所有焊盘电源电流的总和组合来产生比率。 由所有焊盘电源电流的一组比率形成一个n元组，以为不同的跨模变化曲线提供唯一的标记。

公开(公告)号：US20100074040A1

公开(公告)日：2010-03-25

申请号：US12233856

申请日：2008-09-19

申请人： Kanak B. Agarwal ,  Jerry D. Hayes

发明人： Kanak B. Agarwal ,  Jerry D. Hayes

IPC分类号： G11C7/00 ,  G11C5/14

CPC分类号： G11C29/50 ,  G11C29/02 ,  G11C29/025 ,  G11C29/50016 ,  G11C2029/1204 ,  G11C2029/5002

摘要： The present invention provides a method for measuring statistics of dynamic random access memory (DRAM) process parameters for improving yield and performance of a DRAM. The basic principles for measuring capacitance are similar to charge based capacitance (CBCM), however the present invention differs in several fundamental aspects. In one embodiment, the method includes receiving a selection of a storage cell of the DRAM; measuring a storage cell capacitance (Ccell) of the storage cell; measuring a local bitline capacitance (Cbl) of the storage cell; measuring a transfer device voltage (VT) of the storage cell; computing a transfer ratio (TR) for the storage cell; and measuring a data retention time for the storage cell.

摘要翻译： 本发明提供了一种用于测量用于提高DRAM的产量和性能的动态随机存取存储器（DRAM）处理参数的统计量的方法。 测量电容的基本原理类似于基于电荷的电容（CBCM），但是本发明在若干基本方面是不同的。 在一个实施例中，该方法包括接收DRAM的存储单元的选择; 测量存储单元的存储单元电容（Ccell）; 测量存储单元的局部位线电容（Cbl）; 测量存储单元的传送装置电压（VT）; 计算存储单元的传输比（TR）; 并测量存储单元的数据保留时间。

公开(公告)号：US20090102508A1

公开(公告)日：2009-04-23

申请号：US11876100

申请日：2007-10-22

申请人： Kanak B. Agarwal

发明人： Kanak B. Agarwal

IPC分类号： H03K19/00

CPC分类号： H03M11/02 ,  G01R31/2884 ,  G06F11/24

摘要： A pulsed dynamic logic environment metric measurement circuit provides self-referenced, low area/cost and low power measurement of circuit environment metrics, such as supply voltage. A cascade of dynamic logic stages is clocked with a pulse having a width substantially independent of an environment metric to which the delay of the dynamic logic stages is sensitive. The number of dynamic logic stages that evaluate within a given pulse provides a direct measure of the pulse width, and thus the value of the circuit metric. The pulse may be generated from a logical exclusive-OR combination of a clock signal provided from two circuit paths that differ in sensitivity to the environment metric to be measured. One circuit path may have a delay substantially determined only by wire delay, which is not substantially sensitive to circuit environment metrics such as power supply voltage.

摘要翻译： 脉冲动态逻辑环境度量测量电路提供诸如电源电压的电路环境度量的自参考，低面积/成本和低功耗测量。 动态逻辑级的级联用具有基本上不依赖于动态逻辑级的延迟敏感的环境度量的宽度的脉冲来计时。 在给定脉冲内评估的动态逻辑级的数量可以直接测量脉冲宽度，从而提供电路量度的值。 脉冲可以由从要测量的环境度量灵敏度不同的两个电路路径提供的时钟信号的逻辑异或组合产生。 一个电路路径可能具有基本上仅由导线延迟确定的延迟，其不对诸如电源电压的电路环境度量基本上敏感。

公开(公告)号：US20080278182A1

公开(公告)日：2008-11-13

申请号：US11746766

申请日：2007-05-10

申请人： Kanak B. Agarwal ,  Ying Liu ,  Sani R. Nassif

发明人： Kanak B. Agarwal ,  Ying Liu ,  Sani R. Nassif

IPC分类号： G01R27/08

CPC分类号： G01R31/2884 ,  G01R31/31855 ,  H01L22/14 ,  H01L2924/0002 ,  H01L2924/00

摘要： A test structure for measuring resistances of a large number of interconnect elements such as metal, contacts and vias includes an array of test cells in rows and columns. Power is selectively supplied to test cells in a given column while current is selectively steered from test cells in a given row. A first voltage near the power input node of a device under test (DUT) is selectively sensed, and a second voltage near the current measurement tap is selectively sensed. The resistance of the DUT is the difference of the first and second voltages divided by the current. Additional voltage taps are provided for test cells having multiple resistive elements. This array of test cells can be used to characterize the statistical distribution of resistance variation and to identify physical location of defects in resistive elements.

摘要翻译： 用于测量诸如金属，触点和通孔的大量互连元件的电阻的测试结构包括行和列中的测试单元的阵列。 选择性地将功率供给到给定列中的测试单元，同时从给定行中的测试单元选择性地导向电流。 有选择地感测被测设备（DUT）的功率输入节点附近的第一电压，并选择性地感测当前测量分接头附近的第二电压。 DUT的电阻是第一和第二电压除以电流的差值。 为具有多个电阻元件的测试单元提供额外的电压抽头。 这种测试单元阵列可用于表征电阻变化的统计分布，并确定电阻元件中缺陷的物理位置。

公开(公告)号：US07447606B2

公开(公告)日：2008-11-04

申请号：US11551814

申请日：2006-10-23

申请人： Kanak B. Agarwal ,  Sani R. Nassif

发明人： Kanak B. Agarwal ,  Sani R. Nassif

IPC分类号： G01R31/00 ,  G01R31/14

CPC分类号： H01L22/14 ,  H01L29/78

摘要： A IC wafer is fabricated using a process of interest to have a plurality of FET devices with different channel lengths (Leff) form a plurality of channel length groups. The threshold voltage (VT) is measured of a statistical sample of the FET devices in each channel length group at two different drain-to-source voltage (VDS). The mean of VT is calculated for each channel length and each VDS. A slope coefficient λ relating VT to Leff is calculated at each VDS. The total variance of VT is calculated at each VDS. Two equations at each VDS, each relating the total variance of VT to the variance of VT with respect to dopant levels and the square of the slope coefficient λ times the variance of Leff, are solved simultaneously to obtain the variance of VT with respect to dopant levels and the variance of Leff.