公开(公告)号：US20110127633A1

公开(公告)日：2011-06-02

申请号：US12955011

申请日：2010-11-29

申请人： Mary Nadeau ,  Vipulkumar Patel ,  Prakash Gothoskar ,  John Fangman ,  John Matthew Fangman ,  Mark Webster

发明人： Mary Nadeau ,  Vipulkumar Patel ,  Prakash Gothoskar ,  John Fangman ,  John Matthew Fangman ,  Mark Webster

IPC分类号： H01L27/12 ,  B32B3/30 ,  H01L27/04

CPC分类号： G02B7/025 ,  G02B6/4228 ,  G02B6/4239 ,  G02B7/003 ,  H01L23/345 ,  H01L23/544 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2223/54426 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83121 ,  H01L2224/83143 ,  H01L2224/83192 ,  H01L2224/83234 ,  H01L2224/83385 ,  H01L2224/83862 ,  H01L2924/14 ,  Y10T428/24479 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/00

摘要： An arrangement for improving adhesive attachment of micro-components in an assembly utilizes a plurality of parallel-disposed slots formed in the top surface of the substrate used to support the micro-components. The slots are used to control the flow and “shape” of an adhesive “dot” so as to quickly and accurately attach a micro-component to the surface of a substrate. The slots are formed (preferably, etched) in the surface of the substrate in a manner that lends itself to reproducible accuracy from one substrate to another. Other slots (“channels”) may be formed in conjunction with the bonding slots so that extraneous adhesive material will flow into these channels and not spread into unwanted areas.

摘要翻译： 用于改善组件中微组件的粘合附着的装置利用形成在用于支撑微组件的衬底顶表面中的多个平行布置的槽。 这些槽用于控制粘合剂“点”的流动和“形状”，以便将微组件快速且精确地附着在基板的表面上。 在衬底的表面中形成（优选地，蚀刻）狭槽，使其自身具有从一个衬底到另一个衬底的可再现精度。 其它槽（“通道”）可以与结合槽结合形成，使得外来粘合剂材料将流入这些通道并且不会扩散到不需要的区域。

公开(公告)号：US20090162013A1

公开(公告)日：2009-06-25

申请号：US12316540

申请日：2008-12-11

申请人： Mark Webster ,  Vipulkumar Patel ,  Mary Nadeau ,  Prakash Gothoskar ,  David Piede

发明人： Mark Webster ,  Vipulkumar Patel ,  Mary Nadeau ,  Prakash Gothoskar ,  David Piede

IPC分类号： G02B6/42

CPC分类号： G02B6/32 ,  G02B6/305 ,  G02B6/327

摘要： A plasma-based etching process is used to specifically shape the endface of an optical substrate supporting an optical waveguide into a contoured facet which will improve coupling efficiency between the waveguide and a free space optical signal. The ability to use standard photolithographic techniques to pattern and etch the optical endface facet allows for virtually any desired facet geometry to be formed—and replicated across the surface of a wafer for the entire group of assemblies being fabricated. A lens may be etched into the endface using a properly-defined photolithographic mask, with the focal point of the lens selected with respect to the parameters of the optical waveguide and the propagating free space signal. Alternatively, an angled facet may be formed along the endface, with the angle sufficient to re-direct reflected/scattered signals away from the optical axis.

摘要翻译： 使用基于等离子体的蚀刻工艺来将支撑光波导的光学基板的端面特别地成形为轮廓刻面，这将提高波导与自由空间光信号之间的耦合效率。 使用标准光刻技术对光学端面小平面进行图案化和刻蚀的能力允许形成任何所需的刻面几何形状，并跨越制造的整组组件在晶片的表面上复制。 可以使用适当限定的光刻掩模将透镜蚀刻到端面中，相对于光波导的参数和传播的自由空间信号选择透镜的焦点。 或者，可以沿着端面形成成角度的小面，其角度足以将反射/散射信号重新引导远离光轴。

公开(公告)号：US08121450B2

公开(公告)日：2012-02-21

申请号：US12316540

申请日：2008-12-11

申请人： Mark Webster ,  Vipulkumar Patel ,  Mary Nadeau ,  Prakash Gothoskar ,  David Piede

发明人： Mark Webster ,  Vipulkumar Patel ,  Mary Nadeau ,  Prakash Gothoskar ,  David Piede

IPC分类号： G02B6/32 ,  G02B6/26 ,  G02B6/42

CPC分类号： G02B6/32 ,  G02B6/305 ,  G02B6/327

摘要： A plasma-based etching process is used to specifically shape the endface of an optical substrate supporting an optical waveguide into a contoured facet which will improve coupling efficiency between the waveguide and a free space optical signal. The ability to use standard photolithographic techniques to pattern and etch the optical endface facet allows for virtually any desired facet geometry to be formed—and replicated across the surface of a wafer for the entire group of assemblies being fabricated. A lens may be etched into the endface using a properly-defined photolithographic mask, with the focal point of the lens selected with respect to the parameters of the optical waveguide and the propagating free space signal. Alternatively, an angled facet may be formed along the endface, with the angle sufficient to re-direct reflected/scattered signals away from the optical axis.

摘要翻译： 使用基于等离子体的蚀刻工艺来将支撑光波导的光学基板的端面特别地成形为轮廓刻面，这将提高波导与自由空间光信号之间的耦合效率。 使用标准光刻技术对光学端面小平面进行图案化和刻蚀的能力允许形成任何所需的刻面几何形状，并跨越制造的整组组件在晶片的表面上复制。 可以使用适当限定的光刻掩模将透镜蚀刻到端面中，相对于光波导的参数和传播的自由空间信号选择透镜的焦点。 或者，可以沿着端面形成成角度的小面，其角度足以将反射/散射信号重新引导远离光轴。

公开(公告)号：US07697793B2

公开(公告)日：2010-04-13

申请号：US12290285

申请日：2008-10-29

申请人： Mark Webster ,  Vipulkumar Patel ,  Prakash Gothoskar

发明人： Mark Webster ,  Vipulkumar Patel ,  Prakash Gothoskar

IPC分类号： G02B6/12 ,  G02F1/295

CPC分类号： G02F1/025 ,  G02F1/0147 ,  G02F1/225 ,  G02F2201/126

摘要： A silicon-based optical modulator structure includes one or more separate localized heating elements for changing the refractive index of an associated portion of the structure and thereby providing corrective adjustments to address unwanted variations in device performance. Heating is provided by thermo-optic devices such as, for example, silicon-based resistors, silicide resistors, forward-biased PN junctions, and the like, where any of these structures may easily be incorporated with a silicon-based optical modulator. The application of a DC voltage to any of these structures will generate heat, which hen transfers into the waveguiding area. The increase in local temperature of the waveguiding area will, in turn, increase the refractive index of the waveguiding in the area. Control of the applied DC voltage results in controlling the refractive index.

摘要翻译： 基于硅的光学调制器结构包括一个或多个单独的局部加热元件，用于改变结构的相关部分的折射率，从而提供校正调整以解决器件性能的不期望的变化。 加热由诸如硅基电阻器，硅化物电阻器，正向偏置PN结等的热光器件提供，其中这些结构中的任何一个可以容易地与硅基光学调制器结合。 对这些结构中的任一个施加直流电压将产生热量，母鸡转移到波导区域中。 波导区域的局部温度的增加又将增加该区域中波导的折射率。 施加的直流电压的控制导致控制折射率。

公开(公告)号：US20090123114A1

公开(公告)日：2009-05-14

申请号：US12218367

申请日：2008-07-15

申请人： Mark Webster ,  Prakash Gothoskar ,  Vipulkumar Patel ,  David Piede

发明人： Mark Webster ,  Prakash Gothoskar ,  Vipulkumar Patel ,  David Piede

IPC分类号： G02B6/35

CPC分类号： G02B6/30 ,  G02B6/3598 ,  G02B6/3636 ,  G02B6/3652 ,  G02B6/3692 ,  G02B6/4249

摘要： One or more nanotaper coupling waveguides formed within an optical substrate allows for straightforward, reproducible offset launch conditions to be achieved between an incoming signal and the core region of a multimode fiber (which may be disposed along an alignment fixture formed in the optical substrate), fiber array or other multimode waveguiding structure. Offset launching of a single mode signal into a multimode fiber couples the signal into favorable spatial modes which reduce the presence of differential mode dispersion along the fiber. This approach to providing single mode signal coupling into legacy multimode fiber is considered to be an improvement over the prior art which required the use of an interface element between a single mode fiber and multimode fiber, limiting the number of propagating signals and applications for the legacy multimode fiber. An optical switch may be used to select the specific nanotaper(s) for coupling into the multimode fiber.

摘要翻译： 形成在光学衬底内的一个或多个纳米锥耦合波导允许在多模光纤（其可以沿着形成在光学衬底中的对准夹具设置）的入射信号和芯区域之间实现简单，可再现的偏移发射条件， 光纤阵列或其他多模波导结构。 偏移将单模信号发射到多模光纤中将信号耦合到有利的空间模式，这降低了沿着光纤的差分色散的存在。 将单模信号耦合提供给传统多模光纤的这种方法被认为是对需要使用单模光纤和多模光纤之间的接口元件的现有技术的改进，限制了传播信号的数量和遗留的应用 多模光纤 可以使用光学开关来选择用于耦合到多模光纤的特定纳米锥。

公开(公告)号：US20090110342A1

公开(公告)日：2009-04-30

申请号：US12290285

申请日：2008-10-29

申请人： Mark Webster ,  Vipulkumar Patel ,  Prakash Gothoskar

发明人： Mark Webster ,  Vipulkumar Patel ,  Prakash Gothoskar

IPC分类号： G02F1/035

CPC分类号： G02F1/025 ,  G02F1/0147 ,  G02F1/225 ,  G02F2201/126

摘要： A silicon-based optical modulator structure includes one or more separate localized heating elements for changing the refractive index of an associated portion of the structure and thereby providing corrective adjustments to address unwanted variations in device performance. Heating is provided by thermo-optic devices such as, for example, silicon-based resistors, silicide resistors, forward-biased PN junctions, and the like, where any of these structures may easily be incorporated with a silicon-based optical modulator. The application of a DC voltage to any of these structures will generate heat, which then transfers into the waveguiding area. The increase in local temperature of the waveguiding area will, in turn, increase the refractive index of the waveguiding in the area. Control of the applied DC voltage results in controlling the refractive index

摘要翻译： 基于硅的光学调制器结构包括一个或多个单独的局部加热元件，用于改变结构的相关部分的折射率，从而提供校正调整以解决器件性能的不期望的变化。 加热由诸如硅基电阻器，硅化物电阻器，正向偏置PN结等的热光器件提供，其中这些结构中的任何一个可以容易地与硅基光学调制器结合。 对这些结构中的任何一个施加直流电压将产生热量，然后传递到波导区域。 波导区域的局部温度的增加又将增加该区域中波导的折射率。 施加的直流电压的控制导致控制折射率

公开(公告)号：US08836100B2

公开(公告)日：2014-09-16

申请号：US12955011

申请日：2010-11-29

申请人： Mary Nadeau ,  Vipulkumar Patel ,  Prakash Gothoskar ,  John Fangman ,  John Matthew Fangman ,  Mark Webster

发明人： Mary Nadeau ,  Vipulkumar Patel ,  Prakash Gothoskar ,  John Fangman ,  John Matthew Fangman ,  Mark Webster

IPC分类号： H01L23/06 ,  G02B6/38

CPC分类号： G02B7/025 ,  G02B6/4228 ,  G02B6/4239 ,  G02B7/003 ,  H01L23/345 ,  H01L23/544 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2223/54426 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83121 ,  H01L2224/83143 ,  H01L2224/83192 ,  H01L2224/83234 ,  H01L2224/83385 ,  H01L2224/83862 ,  H01L2924/14 ,  Y10T428/24479 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/00

摘要： An arrangement for improving adhesive attachment of micro-components in an assembly utilizes a plurality of parallel-disposed slots formed in the top surface of the substrate used to support the micro-components. The slots are used to control the flow and “shape” of an adhesive “dot” so as to quickly and accurately attach a micro-component to the surface of a substrate. The slots are formed (preferably, etched) in the surface of the substrate in a manner that lends itself to reproducible accuracy from one substrate to another. Other slots (“channels”) may be formed in conjunction with the bonding slots so that extraneous adhesive material will flow into these channels and not spread into unwanted areas.

摘要翻译： 用于改善组件中微组件的粘合附着的装置利用形成在用于支撑微组件的衬底顶表面中的多个平行布置的槽。 这些槽用于控制粘合剂“点”的流动和“形状”，以便将微组件快速且精确地附着在基板的表面上。 在衬底的表面中形成（优选地，蚀刻）狭槽，使其自身具有从一个衬底到另一个衬底的可再现精度。 其它槽（“通道”）可以与结合槽结合形成，使得外来粘合剂材料将流入这些通道并且不会扩散到不需要的区域。

公开(公告)号：US08618625B2

公开(公告)日：2013-12-31

申请号：US13038470

申请日：2011-03-02

申请人： Vipulkumar Patel ,  Prakash Gothoskar ,  Mark Webster ,  Christopher J. Lang

发明人： Vipulkumar Patel ,  Prakash Gothoskar ,  Mark Webster ,  Christopher J. Lang

IPC分类号： H01L31/0224

CPC分类号： H01L31/101 ,  H01L31/1085

摘要： A planar, waveguide-based silicon Schottky barrier photodetector includes a third terminal in the form of a field plate to improve the responsivity of the detector. Preferably, a silicide used for the detection region is formed during a processing step where other silicide contact regions are being formed. The field plate is preferably formed as part of the first or second layer of CMOS metallization and is controlled by an applied voltage to modify the electric field in the vicinity of the detector's silicide layer. By modifying the electric field, the responsivity of the device is “tuned” so as to adjust the momentum of “hot” carriers (electrons or holes, depending on the conductivity of the silicon) with respect to the Schottky barrier of the device. The applied potential functions to align with the direction of momentum of the “hot” carriers in the preferred direction “normal” to the silicon-silicide interface, allowing for an increased number to move over the Schottky barrier and add to the generated photocurrent.

摘要翻译： 平面的基于波导的硅肖特基势垒光电检测器包括场板形式的第三端子，以提高检测器的响应度。 优选地，在其中形成其它硅化物接触区域的处理步骤期间形成用于检测区域的硅化物。 场板优选地形成为第一或第二CMOS金属化层的一部分，并且通过施加的电压来控制，以修改检测器硅化物层附近的电场。 通过修改电场，器件的响应度被“调谐”，以相对于器件的肖特基势垒调节“热”载流子（电子或空穴，取决于硅的导电性）的动量。 所施加的电位功能与“硅”载体的优势方向“正常”硅硅化物界面的动量方向相一致，允许增加的数量移动到肖特基势垒上并增加产生的光电流。

公开(公告)号：US08363986B2

公开(公告)日：2013-01-29

申请号：US13029342

申请日：2011-02-17

申请人： Mark Webster ,  Vipulkumar Patel ,  Prakash Gothoskar ,  David Piede

发明人： Mark Webster ,  Vipulkumar Patel ,  Prakash Gothoskar ,  David Piede

IPC分类号： G02F1/035 ,  G02F1/01 ,  G02B6/26 ,  G02B6/42

CPC分类号： G02B6/12 ,  G02B6/26 ,  G02B26/00 ,  G02F1/025

摘要： A high speed silicon-based optical modulator with control of the dopant profiles in the body and gate regions of the device reduces the series resistance of the structure without incurring substantial optical power loss. That is, the use of increased dopant values in areas beyond the active region will allow for the series resistance to be reduced (and thus increase the modulating speed of the device) without incurring too large a penalty in signal loss. The dopant profiles within the gate and body regions are tailored to exhibit an intermediate value between the high dopant concentration in the contact areas and the low dopant concentration in the carrier integration window area.

摘要翻译： 具有控制器件的主体和栅极区域中的掺杂剂分布的高速硅基光学调制器降低了结构的串联电阻而不会引起实质的光功率损耗。 也就是说，在有源区域之外的区域中使用增加的掺杂剂值将允许降低串联电阻（从而增加器件的调制速度），而不会在信号损失中造成太大的惩罚。 调整栅极和体区内的掺杂剂分布，以显示接触区域中的高掺杂剂浓度与载流子集成窗口区域中的低掺杂剂浓度之间的中间值。

公开(公告)号：US07539358B2

公开(公告)日：2009-05-26

申请号：US11807959

申请日：2007-05-31

申请人： Robert Keith Montgomery ,  Vipulkumar Patel

发明人： Robert Keith Montgomery ,  Vipulkumar Patel

IPC分类号： G02F1/35

CPC分类号： G02F1/025 ,  G02F1/2257

摘要： The surface silicon layer (SOI layer) of an SOI-based optical modulator is processed to exhibit a corrugated surface along the direction of optical signal propagation. The required dielectric layer (i.e., relatively thin “gate oxide”) is formed over the corrugated structure in a manner that preserves the corrugated topology. A second silicon layer, required to form the modulator structure, is then formed over the gate oxide in a manner that follows the corrugated topology, where the overlapping portion of the corrugated SOI layer, gate oxide and second silicon layer defines the active region of the modulator. The utilization of the corrugated active region increases the area over which optical field intensity will overlap with the free carrier modulation region, improving the modulator's efficiency.

摘要翻译： 处理基于SOI的光调制器的表面硅层（SOI层）沿着光信号传播的方向呈现波纹状表面。 所需的电介质层（即相对较薄的“栅极氧化物”）以保持波纹拓扑的方式形成在波纹状结构上。 形成调制器结构所需的第二硅层然后以跟随波纹拓扑的方式形成在栅极氧化物上，其中波纹SOI层，栅极氧化物和第二硅层的重叠部分限定了 调制器。 波纹有源区域的利用增加了光场强度将与自由载波调制区域重叠的面积，从而提高了调制器的效率。