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    SYSTEMS FOR AND METHODS OF MEDICAL SCHEDULING BASED ON SIMULATION-BASED OPTIMIZATION
    2.
    发明申请
    SYSTEMS FOR AND METHODS OF MEDICAL SCHEDULING BASED ON SIMULATION-BASED OPTIMIZATION 审中-公开
    基于模拟优化的医疗调度系统和方法

    公开(公告)号：US20100106517A1

    公开(公告)日：2010-04-29

    申请号：US12257113

    申请日：2008-10-23

    申请人： Mariusz Kociubinski ,  VipulKumar Patel ,  Wilkenson Chua ,  Venkata Mrudula Gullapalli

    发明人： Mariusz Kociubinski ,  VipulKumar Patel ,  Wilkenson Chua ,  Venkata Mrudula Gullapalli

    IPC分类号： G06Q50/00

    CPC分类号： G06Q10/109 ,  G06Q50/22

    摘要： Certain embodiments involve data from places such as healthcare facilities to make predictions about actual expected procedure durations as well as other parameters such as the probability of a patient being late or being a no-show. Before scheduling a patient, the system will use these parameters to run a simulation that can then suggest time slots that maximize target service levels (for example, “patients should not wait longer than 15 minutes in 95% of the cases”) and maximize facility efficiency (minimize the unutilized time between appointments).

    摘要翻译： 某些实施例涉及来自诸如医疗保健设施的地点的数据以对实际预期的过程持续时间以及诸如患者迟发或不显示的概率的其他参数进行预测。 在安排患者之前，系统将使用这些参数来运行模拟，然后可以建议最大化目标服务水平的时段（例如，“患者在95％的病例中不应该等待15分钟以上”），并使设备最大化 效率（尽量减少任用之间未使用的时间）。

    Offset launch mode from nanotaper waveguide into multimode fiber
    3.
    发明授权
    Offset launch mode from nanotaper waveguide into multimode fiber 有权
    从纳米孔波导到多模光纤的偏移发射模式

    公开(公告)号：US07706644B2

    公开(公告)日：2010-04-27

    申请号：US12218367

    申请日：2008-07-15

    申请人： Mark Webster ,  Prakash Gothoskar ,  Vipulkumar Patel ,  David Piede

    发明人： Mark Webster ,  Prakash Gothoskar ,  Vipulkumar Patel ,  David Piede

    IPC分类号： G02B6/26

    CPC分类号： G02B6/30 ,  G02B6/3598 ,  G02B6/3636 ,  G02B6/3652 ,  G02B6/3692 ,  G02B6/4249

    摘要： One or more nanotaper coupling waveguides formed within an optical substrate allows for straightforward, reproducible offset launch conditions to be achieved between an incoming signal and the core region of a multimode fiber (which may be disposed along an alignment fixture formed in the optical substrate), fiber array or other multimode waveguiding structure. Offset launching of a single mode signal into a multimode fiber couples the signal into favorable spatial modes which reduce the presence of differential mode dispersion along the fiber. This approach to providing single mode signal coupling into legacy multimode fiber is considered to be an improvement over the prior art which required the use of an interface element between a single mode fiber and multimode fiber, limiting the number of propagating signals and applications for the legacy multimode fiber. An optical switch may be used to select the specific nanotaper(s) for coupling into the multimode fiber.

    摘要翻译： 形成在光学衬底内的一个或多个纳米锥耦合波导允许在多模光纤（其可以沿着形成在光学衬底中的对准夹具设置）的入射信号和芯区域之间实现简单，可再现的偏移发射条件， 光纤阵列或其他多模波导结构。 偏移将单模信号发射到多模光纤中将信号耦合到有利的空间模式，这降低了沿着光纤的差分色散的存在。 将单模信号耦合提供给传统多模光纤的这种方法被认为是对需要使用单模光纤和多模光纤之间的接口元件的现有技术的改进，限制了传播信号的数量和遗留的应用 多模光纤 可以使用光学开关来选择用于耦合到多模光纤的特定纳米锥。

    Silicon modulator offset tuning arrangement
    4.
    发明授权
    Silicon modulator offset tuning arrangement 有权
    硅调制器偏移调谐布置

    公开(公告)号：US07447395B2

    公开(公告)日：2008-11-04

    申请号：US11810591

    申请日：2007-06-06

    申请人： Robert Keith Montgomery ,  Margaret Ghiron ,  Prakash Gothoskar ,  Paulius Mindaugas Mosinskis ,  Vipulkumar Patel ,  Kalpendu Shastri ,  Mark Webster

    发明人： Robert Keith Montgomery ,  Margaret Ghiron ,  Prakash Gothoskar ,  Paulius Mindaugas Mosinskis ,  Vipulkumar Patel ,  Kalpendu Shastri ,  Mark Webster

    IPC分类号： G02B6/12 ,  G02F1/295

    CPC分类号： G02F1/025 ,  G02F1/0147 ,  G02F1/225 ,  G02F2201/126

    摘要： A silicon-based optical modulator structure includes one or more separate localized heating elements for changing the refractive index of an associated portion of the structure and thereby providing corrective adjustments to address unwanted variations in device performance. Heating is provided by thermo-optic devices such as, for example, silicon-based resistors, silicide resistors, forward-biased PN junctions, and the like, where any of these structures may easily be incorporated with a silicon-based optical modulator. The application of a DC voltage to any of these structures will generate heat, which then transfers into the waveguiding area. The increase in local temperature of the waveguiding area will, in turn, increase the refractive index of the waveguiding in the area. Control of the applied DC voltage results in controlling the refractive index.

    摘要翻译： 基于硅的光学调制器结构包括一个或多个单独的局部加热元件，用于改变结构的相关部分的折射率，从而提供校正调整以解决器件性能的不期望的变化。 加热由诸如硅基电阻器，硅化物电阻器，正向偏置PN结等的热光器件提供，其中这些结构中的任何一种可以容易地与硅基光学调制器结合。 对这些结构中的任何一个施加直流电压将产生热量，然后传递到波导区域。 波导区域的局部温度的增加又将增加该区域中波导的折射率。 施加的直流电压的控制导致控制折射率。

    Vertical stacking of multiple integrated circuits including SOI-based optical components
    6.
    发明申请
    Vertical stacking of multiple integrated circuits including SOI-based optical components 审中-公开
    包括基于SOI的光学元件的多个集成电路的垂直堆叠

    公开(公告)号：US20060177173A1

    公开(公告)日：2006-08-10

    申请号：US11346718

    申请日：2006-02-03

    申请人： Kalpendu Shastri ,  Vipulkumar Patel ,  David Piede ,  John Fangman

    发明人： Kalpendu Shastri ,  Vipulkumar Patel ,  David Piede ,  John Fangman

    IPC分类号： G02B6/12 ,  G02B6/26 ,  G02B6/42 ,  G02B6/10

    CPC分类号： G02B6/42 ,  G02B6/4214 ,  G02B6/43 ,  G02F1/025 ,  H01L31/12

    摘要： A vertical stack of integrated circuits includes at least one CMOS electronic integrated circuit (IC), an SOI-based opto-electronic integrated circuit structure, and an optical input/output coupling element. A plurality of metalized vias may be formed through the thickness of the stack so that electrical connections can be made between each integrated circuit. Various types of optical input/output coupling can be used, such as prism coupling, gratings, inverse tapers, and the like. By separating the optical and electrical functions onto separate ICs, the functionalities of each may be modified without requiring a re-design of the remaining system. By virtue of using SOI-based opto-electronics with the CMOS electronic ICs, a portion of the SOI structure may be exposed to provide access to the waveguiding SOI layer for optical coupling purposes.

    摘要翻译： 集成电路的垂直堆叠包括至少一个CMOS电子集成电路（IC），基于SOI的光电集成电路结构以及光输入/输出耦合元件。 可以通过堆叠的厚度形成多个金属化通孔，使得可以在每个集成电路之间进行电连接。 可以使用各种类型的光输入/输出耦合，例如棱镜耦合，光栅，逆锥等。 通过将光学和电气功能分离到单独的IC上，可以修改每个功能，而不需要重新设计剩余的系统。 通过使用具有CMOS电子IC的基于SOI的光电子器件，SOI结构的一部分可能被暴露以提供对波导SOI层的访问以用于光学耦合目的。

    Wafer-level opto-electronic testing apparatus and method
    9.
    发明申请
    Wafer-level opto-electronic testing apparatus and method 有权
    晶圆级光电测试仪器及方法

    公开(公告)号：US20050194990A1

    公开(公告)日：2005-09-08

    申请号：US11075430

    申请日：2005-03-08

    申请人： Prakash Gothoskar ,  Margaret Ghiron ,  Robert Montgomery ,  Vipulkumar Patel ,  Kalpendu Shastri ,  Soham Pathak ,  David Piede ,  Katherine Yanushefski

    发明人： Prakash Gothoskar ,  Margaret Ghiron ,  Robert Montgomery ,  Vipulkumar Patel ,  Kalpendu Shastri ,  Soham Pathak ,  David Piede ,  Katherine Yanushefski

    IPC分类号： G01R31/26

    CPC分类号： G02B6/30 ,  G02B6/34 ,  G02B2006/12107

    摘要： A wafer-level testing arrangement for opto-electronic devices formed in a silicon-on-insulator (SOI) wafer structure utilizes a single opto-electronic testing element to perform both optical and electrical testing. Beam steering optics may be formed on the testing element and used to facilitate the coupling between optical probe signals and optical coupling elements (e.g., prism couplers, gratings) formed on the top surface of the SOI structure. The optical test signals are thereafter directed into optical waveguides formed in the top layer of the SOI structure. The opto-electronic testing element also comprises a plurality of electrical test pins that are positioned to contact a plurality of bondpad test sites on the opto-electronic device and perform electrical testing operations. The optical test signal results may be converted into electrical representations within the SOI structure and thus returned to the testing element as electrical signals.

    摘要翻译： 用于在绝缘体上硅（SOI）晶片结构中形成的光电器件的晶片级测试装置利用单个光电测试元件执行光学和电学测试。 光束转向光学元件可以形成在测试元件上，并且用于促进光学探针信号与形成在SOI结构的顶表面上的光耦合元件（例如，棱镜耦合器，光栅）之间的耦合。 此后，光学测试信号被引导到形成在SOI结构的顶层中的光波导中。 光电测试元件还包括多个电测试引脚，其被定位成接触光电器件上的多个接合焊盘测试点并执行电测试操作。 光学测试信号结果可以转换为SOI结构内的电气表示，并因此作为电信号返回到测试元件。

    Active manipulation of light in a silicon-on-insulator (SOI) structure
    10.
    发明申请
    Active manipulation of light in a silicon-on-insulator (SOI) structure 有权
    主动操纵绝缘体上硅（SOI）结构中的光

    公开(公告)号：US20050189591A1

    公开(公告)日：2005-09-01

    申请号：US11069852

    申请日：2005-02-28

    申请人： Prakash Gothoskar ,  Margaret Ghiron ,  Robert Montgomery ,  Vipulkumar Patel ,  Kalpendu Shastri ,  Soham Pathak ,  Katherine Yanushefski

    发明人： Prakash Gothoskar ,  Margaret Ghiron ,  Robert Montgomery ,  Vipulkumar Patel ,  Kalpendu Shastri ,  Soham Pathak ,  Katherine Yanushefski

    IPC分类号： G02B6/12 ,  H01L27/15

    CPC分类号： G02B6/12004 ,  G02F1/025 ,  G02F1/292 ,  G02F2001/294

    摘要： An arrangement for actively controlling, in two dimensions, the manipulation of light within an SOI-based optical structure utilizes doped regions formed within the SOI layer and a polysilicon layer of a silicon-insulator-silicon capacitive (SISCAP) structure. The regions are oppositely doped so as to form an active device, where the application of a voltage potential between the oppositely doped regions functions to modify the refractive index in the affected area and alter the properties of an optical signal propagating through the region. The doped regions may be advantageously formed to exhibit any desired “shaped” (such as, for example, lenses, prisms, Bragg gratings, etc.), so as to manipulate the propagating beam as a function of the known properties of these devices. One or more active devices of the present invention may be included within a SISCAP formed, SOI-based optical element (such as, for example, a Mach-Zehnder interferometer, ring resonator, optical switch, etc.) so as to form an active, tunable element.

    摘要翻译： 用于主动地控制SOI基光学结构内的光的操纵的布置利用形成在SOI层内的掺杂区域和硅绝缘体 - 硅电容（SISCAP）结构的多晶硅层。 这些区域相反地掺杂以形成有源器件，其中在相对掺杂区域之间施加电压电位用于改变受影响区域中的折射率并改变传播通过该区域的光信号的特性。 可以有利地形成掺杂区域以呈现任何期望的“成形”（例如，透镜，棱镜，布拉格光栅等），以便根据这些器件的已知特性来操纵传播光束。 本发明的一个或多个有源器件可以包括在形成SISCAP的SOI基光学元件（例如，诸如Mach-Zehnder干涉仪，环形谐振器，光学开关等）中，以形成活跃的 ，可调元素。