公开(公告)号：US20060117232A1

公开(公告)日：2006-06-01

申请号：US10975663

申请日：2004-10-28

Applicant: Robert Warren ,  Paul Huelskamp

Inventor： Robert Warren ,  Paul Huelskamp

IPC: G01R31/28

CPC classification number: G01R31/31723 ,  G01R31/2884 ,  G01R31/31703

Abstract: An apparatus and method are provided for testing integrated circuits. An integrated circuit arrangement is provided having first and second dice. Each die has circuitry for diagnostic testing in response to a diagnostic test signal. The circuitry further defines an input for receiving the diagnostic test signal and an output for transmitting results of the diagnostic testing for each of the dice. Interconnecting circuitry between the dice transmits the diagnostic test signal transmitted to the first die to the second die before the diagnostic testing is completed in the first die.

Abstract translation: 提供了一种用于测试集成电路的装置和方法。 提供具有第一和第二骰子的集成电路装置。 每个管芯具有用于响应于诊断测试信号进行诊断测试的电路。 该电路进一步限定用于接收诊断测试信号的输入端和用于传送针对每个骰子的诊断测试结果的输出。 在诊断测试在第一个模具中完成之前，骰子之间的互连电路将传输到第一裸片的诊断测试信号发送到第二个裸片。

公开(公告)号：US20050253443A1

公开(公告)日：2005-11-17

申请号：US11100096

申请日：2005-04-05

Applicant: Robert Warren ,  Ryan Matzinger

Inventor： Robert Warren ,  Ryan Matzinger

IPC: A47C4/54 ,  A47C7/02 ,  A47C7/72 ,  A47C31/00

CPC classification number: A47C4/54 ,  A47C7/02 ,  A47C7/72 ,  Y10S297/03

Abstract: The present invention provides a seating apparatus having an adjustable level of firmness. The seating apparatus comprises a base, an inflatable element arranged on the base, and a cover covering the inflatable element. Access means in communication with the inflatable element are provided, enabling inflation of the inflatable element for providing an adjustable firmness in the seating area. The inflatable element may comprise a ring having a center opening. The base may comprise a ring having a center opening coinciding with the center opening of the inflatable element. The cover may comprise a section of permeable material over the center opening. A fan may be affixed within the center opening for providing airflow through the center opening.

Abstract translation: 本发明提供一种具有可调节的坚固度的座椅装置。 座椅装置包括基座，布置在基座上的可充气元件和覆盖可膨胀元件的盖子。 提供与充气元件连通的通道装置，使得充气元件的充气能够提供在座位区域中的可调整的坚固度。 可充气元件可以包括具有中心开口的环。 基座可以包括具有与可充气元件的中心开口重合的中心开口的环。 盖可以包括在中心开口上方的可渗透材料的一部分。 风扇可以固定在中心开口内，以提供通过中心开口的气流。

公开(公告)号：US06675284B1

公开(公告)日：2004-01-06

申请号：US09378909

申请日：1999-08-20

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G06F900

CPC classification number: G06F11/267

Abstract: An integrated circuit having a serial data input pin and a serial data output pin, on-chip functional circuitry comprising at least two processing cores, a data adaptor which is in communication with the processing cores by respective communication channels and is connectable to the input and output pins. The data adaptor includes transmit circuitry, including circuitry for receiving parallel data and control signals from on-chip functional circuitry and circuitry for converting parallel data and control signals into a sequence of serial bits including flow control bits, data bits and channel identification bits that identify the communication channel on which parallel data and control signals were received. The adaptor further includes receive circuitry having circuitry for receiving from off-chip via the serial data input pin a sequence of serial bits including flow control bits, data bits and channel identification bits, circuitry for converting the bit sequence into parallel data and control signals for the on-chip functional circuitry and circuitry for transmitting parallel data and control signals on the communication channel identified by said channel identification bits.

Abstract translation: 一种具有串行数据输入引脚和串行数据输出引脚的集成电路，包括至少两个处理核心的片上功能电路，通过各个通信信道与处理核心通信的数据适配器，并且可连接到输入和 输出引脚。 数据适配器包括发射电路，包括用于从片上功能电路接收并行数据和控制信号的电路，以及用于将并行数据和控制信号转换成串行位序列的电路，包括流控制位，数据位和信道识别位， 接收并行数据和控制信号的通信信道。 适配器还包括接收电路，其具有电路，用于经由串行数据输入引脚从片外接收包括流控制位，数据位和信道标识位的串行位序列，用于将位序列转换为并行数据的电路和用于 用于在由所述信道标识位标识的通信信道上发送并行数据和控制信号的片上功能电路和电路。

公开(公告)号：US06279103B1

公开(公告)日：2001-08-21

申请号：US08994358

申请日：1997-12-19

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G06F1100

CPC classification number: G06F11/3636 ,  G06F11/3648

Abstract: There is disclosed a single chip integrated circuit device comprising an instruction trace controller operable to monitor an address in memory of instructions to be executed by an on-chip CPU. The instruction trace controller is connected to trace storage locations for causing selected ones of said addresses to be stored at said trace locations, dependent upon detection that one of said addresses is not the next sequential address in memory after the previous one of the addresses. There is also disclosed a method of providing an instruction trace from an on-chip CPU within a single chip integrated circuit device in which addresses in memory of instructions to be executed by the CPU are held sequentially in an instruction pointer register. The addresses are monitored by an instruction trace controller, which is operable to cause selected ones of the address to be stored at a predetermined trace storage location dependent on detection that one of the addresses is not the next sequential address in memory after the previous one of the addresses.

Abstract translation: 公开了一种单芯片集成电路装置，其包括指令跟踪控制器，该指令跟踪控制器可操作以监视由片上CPU执行的指令的存储器中的地址。 指示跟踪控制器连接到跟踪存储位置，用于使选定的所述地址存储在所述跟踪位置，这取决于检测到所述地址之一不是在前一个地址之后的存储器中的下一个顺序地址。 还公开了一种在单芯片集成电路装置内的片上CPU提供指令轨迹的方法，其中由CPU执行的指令的存储器中的地址将依次保持在指令指针寄存器中。 地址由指令跟踪控制器监视，指令跟踪控制器可操作以使所选地址存储在预定的跟踪存储位置，这取决于检测中的一个地址不是存储器中的之一之后的下一个顺序地址 地址。

公开(公告)号：US5983379A

公开(公告)日：1999-11-09

申请号：US960007

申请日：1997-10-29

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G01R31/28 ,  G01R31/3185 ,  G06F11/22

CPC classification number: G01R31/318555 ,  G01R31/318572

Abstract: There is disclosed a test access port controller for effecting communications across a chip boundary having a test mode and a diagnostic mode of operation, wherein in the test mode of operation the test data is resultant data from a test operation having an expected and time delayed relationship, and in the diagnostic mode of operation diagnostic data is conveyed both on and off chip in the form of respective independent input and output serial bit streams simultaneously through the test access port controller.

Abstract translation: 公开了一种用于实现具有测试模式和诊断操作模式的芯片边界通信的测试访问端口控制器，其中在测试操作模式下，测试数据是来自具有预期和时间延迟关系的测试操作的结果数据 并且在诊断诊断模式下，诊断数据通过测试访问端口控制器同时以相应的独立输入和输出串行比特流的形式传送开和关芯片。

公开(公告)号：US5978870A

公开(公告)日：1999-11-02

申请号：US960750

申请日：1997-10-29

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G06F11/22 ,  G06F9/445 ,  G06F11/14 ,  G06F11/36 ,  G06F15/78 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  G06F13/36

CPC classification number: G06F11/3656 ,  G06F11/1417 ,  G06F9/4401

Abstract: There is disclosed a single chip integrated circuit device having a bus system, functional circuitry, and external port, and a parallel/serial data packet converter interconnecting the bus system and the external port. The parallel/serial data packet converter is operable to convert parallel data from the bus system into bit serial packets for output through the port, and allocate a packet identifier to the bit serial packets in dependence on the information received from the bus system in accordance with a predetermined protocol. A method of effecting communication between a single chip integrated circuit device and an external device using such a parallel/serial data packet converter is also disclosed.

Abstract translation: 公开了具有总线系统，功能电路和外部端口的单芯片集成电路装置，以及将总线系统和外部端口互连的并行/串行数据分组转换器。 并行/串行数据分组转换器可操作以将来自总线系统的并行数据转换为位串行数据包，以通过端口输出，并根据从总线系统接收到的信息，将分组标识符分配给位串行数据包 预定协议。 还公开了使用这种并行/串行数据分组转换器来实现单芯片集成电路器件和外部器件之间的通信的方法。

公开(公告)号：US5742617A

公开(公告)日：1998-04-21

申请号：US518767

申请日：1995-08-24

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G01R31/28 ,  G01R31/3185 ,  G06F11/22

CPC classification number: G01R31/318555 ,  G06F11/2273

Abstract: A test access port controller is provided for implementing scan testing with a chain of scan latches on an integrated circuit. The test access port controller can implement a structural test or a performance test. Selection between the two types of test is achieved through logic circuitry of the test access port controller. An integrated circuit and a test system are also provided.

Abstract translation: 提供了测试访问端口控制器，用于通过集成电路上的一系列扫描锁存器来实现扫描测试。 测试访问端口控制器可以进行结构测试或性能测试。 通过测试访问端口控制器的逻辑电路实现两种测试之间的选择。 还提供集成电路和测试系统。

公开(公告)号：US5719877A

公开(公告)日：1998-02-17

申请号：US519052

申请日：1995-08-24

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G01R31/28 ,  G01R31/3185 ,  G06F11/22 ,  G06F11/267 ,  H03K3/037

CPC classification number: G06F11/2236 ,  G01R31/31858 ,  H03K3/0375

Abstract: A method of testing the performance of a combinational logic circuit is described. In contrast to a structural test which verifies the operation of the combinational logic circuitry, a performance test allows the performance of a combinational logic circuit to be tested by determining the accuracy of a set of outputs resulting from a change in input bits to the combinational logic circuit. Thus, it is possible to monitor more closely performance aspects, such as the maximum delay from input to output of a combination logic circuit.

Abstract translation: 描述了一种测试组合逻辑电路性能的方法。 与验证组合逻辑电路的操作的结构测试相反，性能测试允许通过确定由输入位向组合逻辑的改变而导致的一组输出的精度来测试组合逻辑电路的性能 电路。 因此，可以监视更密切的性能方面，例如从组合逻辑电路的输入到输出的最大延迟。

公开(公告)号：US5719876A

公开(公告)日：1998-02-17

申请号：US519051

申请日：1995-08-24

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G01R31/28 ,  G01R31/3185 ,  G06F11/22 ,  G06F11/267 ,  H03K3/037

CPC classification number: G06F11/2236 ,  G01R31/318541 ,  H03K3/0375

Abstract: A scan latch is described which comprises a capture half-latch, a release half-latch and an update half-latch. The capture half-latch has an input terminal connected to receive an input signal, a control terminal connected to a clock signal, and an output terminal. The release half-latch and update half latch each have an input terminal fixedly connected to the output terminal of the capture half latch. The release half-latch also has a control terminal connected to a clock signal and an scan output terminal. The update half-latch also has a control terminal connected to a clock signal and a data output terminal. The combination of the capture half-latch and one of the update half-latch and the release half-latch acts as a full-latch. The combination of these half-latches allows for simplified circuitry for testing integrated circuits. Clock signals provided to the half-latches can be different clock signals, and their timing can be individually controlled. This scan latch comprising half-latches can be used in place of any full-latch where a scan test is to be carried out and where a functional data output should not change while scan data is being shifted in or out. Furthermore, a scan latch according to this invention is also able to carry out a performance test to test the timing of logic circuitry. A method of using the scan latch to carry out a structural test of a circuit is also described.

Abstract translation: 描述了一种扫描锁存器，其包括捕获半锁存器，释放半锁存器和更新半锁存器。 捕获半锁存器具有连接到输入端的输入端子，连接到时钟信号的控制端子和输出端子。 释放半锁存器和更新半锁存器各自具有固定地连接到捕捉半锁存器的输出端子的输入端子。 释放半锁存器还具有连接到时钟信号和扫描输出端子的控制端子。 更新半锁存器还具有连接到时钟信号和数据输出端子的控制端子。 捕获半锁存器和更新半锁存器和释放半锁存器之一的组合充当完全锁存器。 这些半锁存器的组合允许用于测试集成电路的简化电路。 提供给半锁存器的时钟信号可以是不同的时钟信号，并且它们的时序可以单独控制。 可以使用包括半锁存器的该扫描锁存器代替执行扫描测试的任何完全锁存器，并且当扫描数据被移入或移出时功能数据输出不应该改变。 此外，根据本发明的扫描锁存器还能够执行性能测试以测试逻辑电路的定时。 还描述了使用扫描锁存器来执行电路的结构测试的方法。

公开(公告)号：US5596584A

公开(公告)日：1997-01-21

申请号：US519058

申请日：1995-08-24

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G01R31/28 ,  G01R31/3185 ,  G06F11/267 ,  H03K3/037

CPC classification number: G06F11/2236 ,  G01R31/318541 ,  G01R31/318552 ,  H03K3/0375

Abstract: A half-latch for a scan latch is described. The half-latch has an input terminal for receiving an input signal a first control terminal for receiving a clock signal and an output terminal. When enabled, the half-latch adopts a data transfer state in which it transmits a signal from its input terminal to its output terminal. Alternatively, the half-latch can adopt a data holding state in which a signal is stored on the output terminal, these states being selected in dependence on the state of the clock signal. The half-latch described herein has a second control terminal which receives the control signal to selectively disable the half-latch. This allows a common clock signal to be used when a scan latch is constructed using these half-latches.

Abstract translation: 描述了用于扫描锁存器的半锁存器。 半锁存器具有用于接收输入信号的输入端，用于接收时钟信号的第一控制端和输出端。 当使能时，半锁存器采用数据传输状态，在该状态下，它将信号从其输入端传输到其输出端。 或者，半锁存器可以采用其中信号存储在输出端上的数据保持状态，这些状态根据时钟信号的状态来选择。 本文描述的半锁存器具有第二控制端子，其接收控制信号以选择性地禁用半锁存器。 这允许在使用这些半锁存器构造扫描锁存器时使用公共时钟信号。