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公开(公告)号：US20170068594A1
公开(公告)日：2017-03-09
申请号：US15080307
申请日：2016-03-24
Inventor： Daniele Mangano , Michele Alessandro Carrano , Gaetano Distefano , Antonin Fried
CPC classification number: G06F11/1068 , G06F11/1044 , G11C29/52
Abstract: A method includes: writing first data in a first partition of a first memory module and second data in a first partition of a second memory module, and selectively operating the first and second memory modules in a first operating mode and a second operating mode. The first operating mode includes writing parity bits for the first data in a second partition of the second memory module and parity bits for the second data in a second partition of the first memory module. The second operating mode includes writing further data instead of parity bits in the second partition of one or both the first memory module and the second memory module.
Abstract translation: 一种方法包括：将第一数据存储在第一存储器模块的第一分区中，并将第二数据写入第二存储器模块的第一分区中，并且以第一操作模式和第二操作模式选择性地操作第一和第二存储器模块。 第一操作模式包括在第二存储器模块的第二分区中写入用于第一数据的奇偶校验位和在第一存储器模块的第二分区中写入用于第二数据的奇偶校验位。 第二操作模式包括在第一存储器模块和第二存储器模块中的一个或两个的第二分区中写入另外的数据而不是奇偶校验位。
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62.发明申请公开(公告)号：US20140344485A1
公开(公告)日：2014-11-20
申请号：US14278403
申请日：2014-05-15
Applicant: STMicroelectronics S.r.l.
Inventor： Mirko Dondini , Daniele Mangano , Giuseppe Falconeri
IPC: G06F13/28
CPC classification number: G06F13/28
Abstract: A communication system is arranged to interface a plurality of transmission circuits with an interconnection network. Each transmission circuit generates read requests and/or write requests. The communication system includes a first circuit that operates independently of the communication protocol of the interconnection network. In particular, the first circuit includes, a) for each transmission circuit a communication interface configured for receiving the read requests and/or write requests from the respective transmission circuit, b) a segmentation circuit configured for dividing, i.e., segmenting, the read requests and/or write requests received from the transmission circuits into transfer segments, and c) an interleaving circuit configured for generating, via an operation of interleaving of the transfer segments, a series of segments. The communication system also includes a second circuit configured for converting the transfer segments of the series of segments into data packets according to the protocol of the interconnection network and for transmitting the data packets to the interconnection network.
Abstract translation: 通信系统被布置为将多个传输电路与互连网络接口。 每个传输电路产生读请求和/或写请求。 通信系统包括独立于互连网络的通信协议操作的第一电路。 特别地，第一电路包括：a）对于每个传输电路，配置用于从各个传输电路接收读取请求和/或写入请求的通信接口，b）分配电路，被配置为将读取请求 和/或将从所述传输电路接收的请求写入传输段，以及c）被配置为经由所述传送段的交织操作生成一系列段的交织电路。 通信系统还包括第二电路，其被配置为根据互连网络的协议将一系列段的传输段转换成数据包，并将数据包发送到互连网络。
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公开(公告)号：US20130259146A1
公开(公告)日：2013-10-03
申请号：US13854419
申请日：2013-04-01
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Daniele Mangano , Salvatore Pisasale , Carmelo Pistritto
CPC classification number: H03M13/6522 , G06F13/4286 , H03M13/51
Abstract: A completion-detector circuit for detecting completion of the transfer of asynchronous data on a communication channel with signal lines organized according to a delay-insensitive encoding (e.g., dual-rail, m-of-n, Berger encoding) comprises: logic circuitry for detecting the data on the aforesaid signal lines configured for: i) producing a first signal indicating the fact that the asynchronous data on the signal lines are stable; ii) producing a second signal indicating the fact that the signal lines are de-asserted; and an asynchronous finite-state machine supplied with the first signal and the second signal for producing a signal of detection of completion of transfer of the asynchronous data, the detection signal having: a first value, when the first signal is asserted; and a second value, when the second signal is asserted; and being on hold when neither one nor the other of said first signal and said second signal is asserted.
Abstract translation: 一种完成检测器电路，用于检测在根据延迟不敏感编码（例如，双轨，m-of-n，Berger编码）组织的信号线在通信信道上完成异步数据的传输，包括：用于 检测上述信号线上的数据，其配置用于：i）产生指示信号线上的异步数据是稳定的事实的第一信号; ii）产生指示信号线被断言的事实的第二信号; 以及提供有第一信号和第二信号的异步有限状态机，用于产生检测异步数据传输完成的信号，检测信号具有：第一值，当第一信号被断言时; 以及第二值，当所述第二信号被断言时; 并且当所述第一信号和所述第二信号的一个或另一个被断言时，它们处于保持状态。
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公开(公告)号：US11906994B2
公开(公告)日：2024-02-20
申请号：US17836524
申请日：2022-06-09
Inventor： Daniele Mangano , Andrei Tudose , Francesco Clerici , Pasquale Butta'
IPC: G06F1/00 , G05F1/46 , G06F1/3296
CPC classification number: G05F1/468 , G06F1/3296
Abstract: A voltage regulator is embedded in a circuit intermediate a first node (coupled to a battery) and a second node (supplying power to an external memory). The voltage regulator is activatable in a first mode of operation for startup during which an voltage is applied to the second node that increases towards a supply threshold. In response to the voltage at the second node reaching the supply threshold, the voltage regulator transitions to a second mode of operation where a programmable regulated voltage (higher than the supply threshold) is applied to the second node. In response to receipt of a low-power operation request, a first high-drive regulator circuitry is deactivated and a second low-power regulator circuitry is activated to provide a third mode of operation at low power.
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公开(公告)号：US11543842B2
公开(公告)日：2023-01-03
申请号：US16803942
申请日：2020-02-27
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Mirko Dondini , Daniele Mangano , Riccardo Condorelli
IPC: G05F1/00 , G05F1/575 , G05B19/042 , G06F13/40 , H03B5/32 , H03K19/17736
Abstract: An integrated circuit includes a clock control circuit coupled to a reference clock signal node and a plurality of circuits including a voltage regulator, a digital circuit, and an analog circuit. The voltage regulator, in operation, supplies a regulated voltage. The clock control circuit, in operation, generates a system clock. Input/output interface circuitry is coupled to the plurality of circuits and a common input/output node. The input/output interface circuitry, in operation, selectively couples one of the plurality of circuits to the common input/output node.
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Patent Agency Ranking
公开(公告)号：US20210278868A1
公开(公告)日：2021-09-09
申请号：US16810639
申请日：2020-03-05
Inventor： Michel Cuenca , Bruno Gailhard , Daniele Mangano
IPC: G05F1/56
Abstract: In an embodiment, a method includes: receiving a main supply voltage; generating a first regulated output voltage with a DC-DC converter; providing the main supply voltage to a driver of a control terminal of an output transistor of an LDO; receiving, at an input terminal of the LDO, the first regulated output voltage; generating, at an output terminal of the LDO, a second regulated output voltage from the first regulated output voltage; and when the main supply voltage falls below a predetermined threshold, discharging a capacitor coupled to the input terminal of the LDO by activating a switch coupled to the input terminal of the LDO.
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公开(公告)号：US10985736B2
公开(公告)日：2021-04-20
申请号：US16894640
申请日：2020-06-05
Inventor： Daniele Mangano , Roland Van Der Tuijn , Pasquale Butta′
Abstract: An embodiment device comprises a processing circuit and IP circuitry coupled to a power supply line, wherein the IP circuitry has an IP circuitry supply threshold for IP circuitry operation. A supply monitor circuit is coupled to the power supply line to sense the voltage on the power supply line and to switch the processing circuit to a low-power mode as a result of a drop in the voltage on the power supply line. The supply monitor circuit comprises a threshold setting node and is configured to be deactivated as a result of the voltage on the power supply line dropping below a deactivation threshold level set at the threshold setting node. A threshold setting circuit is configured to apply to the threshold setting node of the supply monitor circuit the IP circuitry supply threshold as a result of the processing circuit being in the low-power mode.
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公开(公告)号：US10168443B2
公开(公告)日：2019-01-01
申请号：US14835935
申请日：2015-08-26
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Daniele Mangano , Riccardo Condorelli
Abstract: A system for interfacing an LC sensor includes a starter configured to selectively start an oscillation of the LC sensor. The system also includes an analog peak detector configured to determine a signal (Vpeak) being indicative of a peak voltage of the oscillation of the LC sensor and a detector configured to determine a state of the LC sensor as a function of the signal (Vpeak) determined by the analog peak detector.
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公开(公告)号：US09959226B2
公开(公告)日：2018-05-01
申请号：US14841522
申请日：2015-08-31
Applicant: STMicroelectronics S.R.L.
Inventor： Daniele Mangano , Mirko Dondini , Salvatore Pisasale
CPC classification number: G06F13/28 , G06F3/0619 , G06F3/0655 , G06F3/067 , G06F13/4059 , G06F2213/0038
Abstract: A communication interface couples a transmission circuit with an interconnection network. The transmission circuit requests transmission of a predetermined amount of data. The communication interface receives data segments from the transmission circuit, stores the data segments in a memory, and verifies whether the memory contains the predetermined amount of data. In the case where the memory contains the predetermined amount of data, the communication interface starts transmission of the data stored in the memory. Alternatively, in the case where the memory contains an amount of data less than the predetermined amount of data, the communication interface determines a parameter that identifies the time that has elapsed since the transmission request or the first datum was received from the aforesaid transmission circuit, and verifies whether the time elapsed exceeds a time threshold. In the case where the time elapsed exceeds the time threshold, the communication interface starts transmission of the data stored in the memory.
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公开(公告)号：US09823965B2
公开(公告)日：2017-11-21
申请号：US15080307
申请日：2016-03-24
Inventor： Daniele Mangano , Michele Alessandro Carrano , Gaetano Di Stefano , Antonin Fried
CPC classification number: G06F11/1068 , G06F11/1044 , G11C29/52
Abstract: A method includes: writing first data in a first partition of a first memory module and second data in a first partition of a second memory module, and selectively operating the first and second memory modules in a first operating mode and a second operating mode. The first operating mode includes writing parity bits for the first data in a second partition of the second memory module and parity bits for the second data in a second partition of the first memory module. The second operating mode includes writing further data instead of parity bits in the second partition of one or both the first memory module and the second memory module.
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