公开(公告)号：US6114210A

公开(公告)日：2000-09-05

申请号：US979364

申请日：1997-11-26

Applicant: David Wu ,  Scott Luning

Inventor： David Wu ,  Scott Luning

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/26586 ,  H01L29/66659 ,  H01L29/7835

Abstract: A CMOS semiconductor device is formed having an N-channel transistor comprising a drain region with a graded N-LDD junction. The graded N-LDD junction is obtained by plural ion implantations at different implantation dosages, energies and angles. The graded N-LDD junction reduces the electric field around the drain, thereby increasing the HCI lifetime without adversely impacting the short channel effect.

Abstract translation: 形成具有N沟道晶体管的CMOS半导体器件，N沟道晶体管包括具有渐变N-LDD结的漏极区。 通过以不同植入剂量，能量和角度的多个离子注入获得分级N-LDD结。 分级N-LDD结降低了漏极周围的电场，从而提高了HCl寿命，而不会对短沟道效应产生不利影响。

公开(公告)号：US5952693A

公开(公告)日：1999-09-14

申请号：US923996

申请日：1997-09-05

Applicant: David Wu ,  Scott Luning

Inventor： David Wu ,  Scott Luning

IPC: H01L21/265 ,  H01L21/336 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L27/092 ,  H01L29/6656 ,  H01L29/7833 ,  H01L21/2652 ,  Y10S257/917

Abstract: A CMOS semiconductor device is formed having an N-channel transistor comprising a graded junction with reduced junction capacitance. The graded junction is achieved by forming a second sidewall spacer on the gate electrode, after source/drain implantations, and ion-implanting an N-type impurity with high diffusivity, e.g., P into an A.sub.5 implant, followed by activation annealing.

公开(公告)号：US5650343A

公开(公告)日：1997-07-22

申请号：US474301

申请日：1995-06-07

Applicant: Scott Luning ,  Roger Alvis

Inventor： Scott Luning ,  Roger Alvis

IPC: H01L21/266 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/49 ,  H01L29/78 ,  H01L21/265

CPC classification number: H01L29/66598 ,  H01L21/266 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/823468 ,  H01L29/0847 ,  H01L29/4966 ,  H01L29/6659 ,  H01L29/7833

Abstract: A process for forming shallow and/or lightly doped regions of impurity concentration adjacent to source/drain semiconductor regions in a semiconductor device. In one embodiment, the invention comprises: (a) providing a semiconductor of a first conductivity type having a first surface; (b) forming a gate structure on said first surface, the gate structure including a gate oxide layer and a polysilicon layer, and a ledge; and (c) implanting an impurity of a second conductivity type into the material and the ledge whereby a portion of the implant enters the substrate after passing through the ledge area overlying the edge of the gate and enters the substrate to a first depth below the surface, while a second portion of the implant does not pass through the ledge and enters the substrate to a depth below the surface of the substrate deeper than the first portion. In addition, an apparatus is disclosed, The apparatus may include a substrate having a surface; an insulating layer on the surface of the substrate, having a surface; a gate material layer on the surface of the insulating layer, the gate material layer having a surface; and an overhanging ledge comprised of an etchable material, having a thickness sufficient to permit at least a portion of a dopant implant to penetrate said overhanging ledge provided on the surface of the gate material layer.

Abstract translation: 一种用于在半导体器件中形成与源极/漏极半导体区域相邻的杂质浓度的浅和/或轻掺杂区域的工艺。 在一个实施例中，本发明包括：（a）提供具有第一表面的第一导电类型的半导体; （b）在所述第一表面上形成栅极结构，所述栅极结构包括栅极氧化物层和多晶硅层，以及栅极; 并且（c）将第二导电类型的杂质注入到所述材料和所述凸缘中，从而一部分所述注入物在通过所述凸缘区域之后进入所述衬底，所述凸缘区域覆盖所述栅极的边缘并且进入所述衬底到所述表面下方的第一深度 而植入物的第二部分不通过突出部并且进入衬底至比第一部分更深的衬底表面下方的深度。 此外，公开了一种装置。该装置可以包括具有表面的基板; 在基板的表面上具有表面的绝缘层; 所述绝缘层的表面上的栅极材料层，所述栅极材料层具有表面; 以及由可蚀刻材料组成的悬垂凸缘，其具有足以允许至少一部分掺杂剂注入物穿过设置在栅极材料层的表面上的所述悬垂凸缘的厚度。

公开(公告)号：US5646448A

公开(公告)日：1997-07-08

申请号：US699821

申请日：1996-08-19

Applicant: Richard K. Klein ,  Darrell Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

Inventor： Richard K. Klein ,  Darrell Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76805 ,  H01L21/76877 ,  Y10S257/915 ,  Y10S438/927

Abstract: A multilayer semiconductor structure includes a conductive via. The conductive via includes a pellet of metal having a high resistance to electromigration. The pellet is made from a conformal layer of copper or gold deposited over the via to form a copper or gold reservoir or contact located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the pellet from diffusing into the insulating layer. The pellet can be formed by selective deposition or by etching a conformal layer. The conformal layer can be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and pellet may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.

Abstract translation: 多层半导体结构包括导电通孔。 导电通孔包括具有高抗电迁移性的金属颗粒。 沉淀物由沉积在通孔上的铜或金的保形层制成，以形成位于通孔中的铜或金储存器或触点。 在储存器和绝缘层之间设置阻挡层以防止颗粒扩散到绝缘层中。 颗粒可以通过选择性沉积或通过蚀刻保形层形成。 可以通过溅射，准直溅射，化学气相沉积（CVD），浸渍，蒸发或其它方式沉积共形层。 可以通过各向异性干蚀刻，等离子体辅助蚀刻或其它层去除技术来蚀刻阻挡层和颗粒。