公开(公告)号：US5935867A

公开(公告)日：1999-08-10

申请号：US481895

申请日：1995-06-07

Applicant: Roger Alvis ,  Scott Luning ,  Peter Griffin

Inventor： Roger Alvis ,  Scott Luning ,  Peter Griffin

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66659 ,  H01L21/26586 ,  H01L29/7835

Abstract: A process for forming a shallow, lightly doped region in a semiconductor device. The method comprises the steps of providing a semiconductor substrate having a surface; growing an oxide layer on the substrate, the oxide having a thickness; depositing a layer of polysilicon on the oxide; patterning the polysilicon layer and the oxide layer to provide a gate structure; and implanting into the substrate a source and a drain region about the gate structure at an angle less than 90 degrees with respect to the surface of the substrate.

Abstract translation: 一种用于在半导体器件中形成浅的，轻掺杂区域的工艺。 该方法包括提供具有表面的半导体衬底的步骤; 在衬底上生长氧化物层，氧化物具有厚度; 在氧化物上沉积多晶硅层; 图案化多晶硅层和氧化物层以提供栅极结构; 以及相对于所述衬底的表面以小于90度的角度将围绕所述栅极结构的源极和漏极区域注入到所述衬底中。

公开(公告)号：US5650343A

公开(公告)日：1997-07-22

申请号：US474301

申请日：1995-06-07

Applicant: Scott Luning ,  Roger Alvis

Inventor： Scott Luning ,  Roger Alvis

IPC: H01L21/266 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/49 ,  H01L29/78 ,  H01L21/265

CPC classification number: H01L29/66598 ,  H01L21/266 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/823468 ,  H01L29/0847 ,  H01L29/4966 ,  H01L29/6659 ,  H01L29/7833

Abstract: A process for forming shallow and/or lightly doped regions of impurity concentration adjacent to source/drain semiconductor regions in a semiconductor device. In one embodiment, the invention comprises: (a) providing a semiconductor of a first conductivity type having a first surface; (b) forming a gate structure on said first surface, the gate structure including a gate oxide layer and a polysilicon layer, and a ledge; and (c) implanting an impurity of a second conductivity type into the material and the ledge whereby a portion of the implant enters the substrate after passing through the ledge area overlying the edge of the gate and enters the substrate to a first depth below the surface, while a second portion of the implant does not pass through the ledge and enters the substrate to a depth below the surface of the substrate deeper than the first portion. In addition, an apparatus is disclosed, The apparatus may include a substrate having a surface; an insulating layer on the surface of the substrate, having a surface; a gate material layer on the surface of the insulating layer, the gate material layer having a surface; and an overhanging ledge comprised of an etchable material, having a thickness sufficient to permit at least a portion of a dopant implant to penetrate said overhanging ledge provided on the surface of the gate material layer.

Abstract translation: 一种用于在半导体器件中形成与源极/漏极半导体区域相邻的杂质浓度的浅和/或轻掺杂区域的工艺。 在一个实施例中，本发明包括：（a）提供具有第一表面的第一导电类型的半导体; （b）在所述第一表面上形成栅极结构，所述栅极结构包括栅极氧化物层和多晶硅层，以及栅极; 并且（c）将第二导电类型的杂质注入到所述材料和所述凸缘中，从而一部分所述注入物在通过所述凸缘区域之后进入所述衬底，所述凸缘区域覆盖所述栅极的边缘并且进入所述衬底到所述表面下方的第一深度 而植入物的第二部分不通过突出部并且进入衬底至比第一部分更深的衬底表面下方的深度。 此外，公开了一种装置。该装置可以包括具有表面的基板; 在基板的表面上具有表面的绝缘层; 所述绝缘层的表面上的栅极材料层，所述栅极材料层具有表面; 以及由可蚀刻材料组成的悬垂凸缘，其具有足以允许至少一部分掺杂剂注入物穿过设置在栅极材料层的表面上的所述悬垂凸缘的厚度。

公开(公告)号：US08193592B2

公开(公告)日：2012-06-05

申请号：US12904662

申请日：2010-10-14

Applicant: Frank Bin Yang ,  Andrew M. Waite ,  Scott Luning

Inventor： Frank Bin Yang ,  Andrew M. Waite ,  Scott Luning

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L21/26586 ,  H01L29/66659 ,  H01L29/7834 ,  H01L2924/0002 ,  Y10S438/931 ,  H01L2924/00

Abstract: A method for fabricating a MOSFET (e.g., a PMOS FET) includes providing a semiconductor substrate having surface characterized by a (110) surface orientation or (110) sidewall surfaces, forming a gate structure on the surface, and forming a source extension and a drain extension in the semiconductor substrate asymmetrically positioned with respect to the gate structure. An ion implantation process is performed at a non-zero tilt angle. At least one spacer and the gate electrode mask a portion of the surface during the ion implantation process such that the source extension and drain extension are asymmetrically positioned with respect to the gate structure by an asymmetry measure.

Abstract translation: 一种用于制造MOSFET（例如，PMOS FET）的方法包括提供具有由（110）表面取向或（110）侧壁表面表征的表面的半导体衬底，在表面上形成栅极结构，并形成源延伸和 半导体衬底中的漏极延伸部相对于栅极结构非对称地定位。 以非零倾角进行离子注入工艺。 在离子注入过程期间，至少一个间隔物和栅电极掩盖表面的一部分，使得源极延伸和漏极延伸通过不对称度量相对于栅极结构不对称地定位。

公开(公告)号：US08148214B2

公开(公告)日：2012-04-03

申请号：US12360961

申请日：2009-01-28

Applicant: Andrew M. Waite ,  Scott Luning

Inventor： Andrew M. Waite ,  Scott Luning

IPC: H01L21/00

CPC classification number: H01L29/6656 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

Abstract: A stressed field effect transistor and methods for its fabrication are provided. The field effect transistor comprises a silicon substrate with a gate insulator overlying the silicon substrate. A gate electrode overlies the gate insulator and defines a channel region in the silicon substrate underlying the gate electrode. A first silicon germanium region having a first thickness is embedded in the silicon substrate and contacts the channel region. A second silicon germanium region having a second thickness greater than the first thickness and spaced apart from the channel region is also embedded in the silicon substrate.

Abstract translation: 提供了一种应力场效应晶体管及其制造方法。 场效应晶体管包括具有覆盖硅衬底的栅极绝缘体的硅衬底。 栅电极覆盖栅极绝缘体，并且在栅电极下面的硅衬底中限定沟道区。 具有第一厚度的第一硅锗区域嵌入在硅衬底中并与沟道区域接触。 具有大于第一厚度并且与沟道区间隔开的第二厚度的第二硅锗区域也嵌入在硅衬底中。

公开(公告)号：US20110062498A1

公开(公告)日：2011-03-17

申请号：US12561685

申请日：2009-09-17

Applicant: Frank (Bin) Yang ,  Johan W. Weijtmans ,  Scott Luning

Inventor： Frank (Bin) Yang ,  Johan W. Weijtmans ,  Scott Luning

IPC: H01L29/772 ,  H01L21/335

CPC classification number: H01L29/665 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: Semiconductor devices with embedded silicon germanium source/drain regions are formed with enhanced channel mobility, reduced contact resistance, and reduced silicide encroachment. Embodiments include embedded silicon germanium source/drain regions with a first portion having a relatively high germanium concentration, e.g., about 25 to about 35 at. %, an overlying second portion having a first layer with a relatively low germanium concentration, e.g., about 10 to about 20 at. %, and a second layer having a germanium concentration greater than that of the first layer. Embodiments include forming additional layers on the second layer, each odd numbered layer having relatively low germanium concentration, at. % germanium, and each even numbered layer having a relatively high germanium concentration. Embodiments include forming the first region at a thickness of about 400 Å to 28 about 800 Å, and the first and second layers at a thickness of about 30 Å to about 70 Å.

Abstract translation: 具有嵌入式硅锗源极/漏极区域的半导体器件形成具有增强的沟道迁移率，降低的接触电阻和减少的硅化物侵蚀。 实施例包括具有较高锗浓度的第一部分的嵌入式硅锗源/漏区，例如约25至约35at。 ％，上覆的第二部分具有具有相对低的锗浓度的第一层，例如约10至约20at。 ％，第二层的锗浓度大于第一层的浓度。 实施例包括在第二层上形成附加层，每个奇数层具有较低的锗浓度。 ％锗，并且每个偶数层具有较高的锗浓度。 实施例包括形成厚度为约400至28约800的第一区域，第一和第二层的厚度为约至大约为70埃。

公开(公告)号：US07893493B2

公开(公告)日：2011-02-22

申请号：US11456326

申请日：2006-07-10

Applicant: Yun-Yu Wang ,  Linda Black ,  Judson R. Holt ,  Woo-Hyeong Lee ,  Scott Luning ,  Christopher D. Sheraw

Inventor： Yun-Yu Wang ,  Linda Black ,  Judson R. Holt ,  Woo-Hyeong Lee ,  Scott Luning ,  Christopher D. Sheraw

IPC: H01L27/12 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/02639 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/84

Abstract: An intermediate hybrid surface orientation structure may include a silicon-on-insulator (SOI) substrate adhered to a bulk silicon substrate, the silicon of the SOI substrate having a different surface orientation than that of the bulk silicon substrate, and a reachthrough region extending through the SOI substrate to the bulk silicon substrate, the reachthrough region including a silicon nitride liner over a silicon oxide liner and a silicon epitaxially grown from the bulk silicon substrate, the epitaxially grown silicon extending into an undercut into the silicon oxide liner under the silicon nitride liner, wherein the epitaxially grown silicon is substantially stacking fault free.

Abstract translation: 中间混合表面取向结构可以包括粘附到体硅衬底上的绝缘体上硅（SOI）衬底，SOI衬底的硅具有与体硅衬底不同的表面取向，并且穿透区域延伸穿过 SOI衬底到体硅衬底，穿透区域包括在氧化硅衬底上的氮化硅衬垫和从体硅衬底外延生长的硅，外延生长的硅延伸到底切到氮化硅之下的氧化硅衬底中 衬垫，其中外延生长的硅基本上是无层错的。

公开(公告)号：US07674720B2

公开(公告)日：2010-03-09

申请号：US12131214

申请日：2008-06-02

Applicant: Yun-Yu Wang ,  Linda Black ,  Judson R. Holt ,  Woo-Hyeong Lee ,  Scott Luning ,  Christopher D. Sheraw

Inventor： Yun-Yu Wang ,  Linda Black ,  Judson R. Holt ,  Woo-Hyeong Lee ,  Scott Luning ,  Christopher D. Sheraw

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/02639 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/84

Abstract: Methods are disclosed for providing stacking fault reduced epitaxially grown silicon for use in hybrid surface orientation structures. In one embodiment, a method includes depositing a silicon nitride liner over a silicon oxide liner in an opening, etching to remove the silicon oxide liner and silicon nitride liner on a lower surface of the opening, undercutting the silicon nitride liner adjacent to the lower surface, and epitaxially growing silicon in the opening. The silicon is substantially reduced of stacking faults because of the negative slope created by the undercut.

Abstract translation: 公开了用于提供用于混合表面取向结构的堆叠故障减少的外延生长的硅的方法。 在一个实施例中，一种方法包括在开口中的氧化硅衬垫上沉积氮化硅衬垫，蚀刻以除去开口的下表面上的氧化硅衬垫和氮化硅衬垫，将邻近下表面的氮化硅衬垫 并且在开口中外延生长硅。 由于底切产生的负斜率，硅片堆积层错误大大减少。

公开(公告)号：US07223662B2

公开(公告)日：2007-05-29

申请号：US11082122

申请日：2005-03-16

Applicant: Thorsten Kammler ,  Scott Luning ,  Linda Black

Inventor： Thorsten Kammler ,  Scott Luning ,  Linda Black

IPC: H01L21/336 ,  H01L21/44 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/26506 ,  H01L21/28035 ,  H01L29/41783 ,  H01L29/42384 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66772

Abstract: By substantially amorphizing a selectively epitaxially grown silicon layer used for forming a raised drain and source region and a portion of the underlying substrate, or just the surface region of the substrate (prior to growing the silicon overlayer), the number of interface defects located between the grown silicon layer and the initial substrate surface may be significantly reduced. Consequently, deleterious effects such as charge carrier gettering or creating diffusion paths for dopants may be suppressed.

Abstract translation: 通过使用于形成隆起的漏极和源极区域以及下部衬底的一部分或仅仅衬底的表面区域（在生长硅覆盖层之前）的选择性外延生长的硅层基本上非晶化，位于 可以显着减少生长的硅层和初始衬底表面。 因此，可以抑制诸如电荷载体吸杂或产生掺杂剂的扩散路径的有害影响。

公开(公告)号：US20060252191A1

公开(公告)日：2006-11-09

申请号：US11120857

申请日：2005-05-03

Applicant: Thorsten Kammler ,  Helmut Bierstedt ,  Scott Luning

Inventor： Thorsten Kammler ,  Helmut Bierstedt ,  Scott Luning

IPC: H01L21/8234 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L29/7833 ,  H01L21/0206 ,  H01L21/823814 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/78621

Abstract: A first gate structure and a second gate structure are formed overlying a semiconductor substrate. A first protective layer is formed overlying the first gate structure and an associate source drain region. A first epitaxial layer is formed overlying the second source drain prior to removal of the first protective layer.

Abstract translation: 第一栅极结构和第二栅极结构形成在半导体衬底上。 第一保护层形成在第一栅极结构和相关源极漏极区之上。 在去除第一保护层之前，在第二源极漏极上形成第一外延层。

公开(公告)号：US20060003533A1

公开(公告)日：2006-01-05

申请号：US11082122

申请日：2005-03-16

Applicant: Thorsten Kammler ,  Scott Luning ,  Linda Black

Inventor： Thorsten Kammler ,  Scott Luning ,  Linda Black

IPC: H01L21/336 ,  H01L21/425

CPC classification number: H01L21/26506 ,  H01L21/28035 ,  H01L29/41783 ,  H01L29/42384 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66772

Abstract: By substantially amorphizing a selectively epitaxially grown silicon layer used for forming a raised drain and source region and a portion of the underlying substrate, or just the surface region of the substrate (prior to growing the silicon overlayer), the number of interface defects located between the grown silicon layer and the initial substrate surface may be significantly reduced. Consequently, deleterious effects such as charge carrier gettering or creating diffusion paths for dopants may be suppressed.

Abstract translation: 通过使用于形成隆起的漏极和源极区域以及下部衬底的一部分或仅仅衬底的表面区域（在生长硅覆盖层之前）的选择性外延生长的硅层基本上非晶化，位于 可以显着减少生长的硅层和初始衬底表面。 因此，可以抑制诸如电荷载体吸杂或产生掺杂剂的扩散路径的有害影响。