公开(公告)号：US10559321B1

公开(公告)日：2020-02-11

申请号：US16274669

申请日：2019-02-13

Applicant: Seagate Technology LLC

Inventor： Zheng Wu ,  Jason Bellorado ,  Marcus Marrow ,  Vincent B Ashe

IPC: G11B5/09 ,  G11B20/10

Abstract: In one implementation, the disclosure provides a system including a first circuit to compute a timing error based on a received error signal and an estimated interference signal and a timing loop filter to output a frequency offset and a phase shift based on the timing error received as input. The system also includes a phase accumulator to accumulate at least a phase shift to generate a sample index and phase and an interpolation filter to generate samples of a side track signal using the sample index and phase.

公开(公告)号：US10469290B1

公开(公告)日：2019-11-05

申请号：US15800738

申请日：2017-11-01

Applicant: Seagate Technology LLC

Inventor： Marcus Marrow ,  Jason Bellorado

IPC: H04L25/03

Abstract: An apparatus may include a circuit configured to process at least one input signal using a set of channel parameters. The circuit may adapt, using a regularized adaptation algorithm, a first set of channel parameters for use by the circuit as the set of channel parameters in processing the at least one input signal, the regularized adaptation algorithm penalizing deviations by the first set of channel parameters from a corresponding predetermined second set of channel parameters. The circuit may then perform the processing of the at least one input signal using the first set of channel parameters as the set of channel parameters.

公开(公告)号：US20180366155A1

公开(公告)日：2018-12-20

申请号：US15791190

申请日：2017-10-23

Applicant: Seagate Technology LLC

Inventor： Jason Bellorado ,  Marcus Marrow ,  Zheng Wu

IPC: G11B20/10 ,  H03K5/131 ,  H04L7/00

Abstract: An apparatus may include a circuit configured to receive a first phase control value of a phase control value signal, generate a first phase interpolator control signal value of a phase interpolator control signal and generate a first digital interpolator control signal value of a digital interpolator control signal. The apparatus may further be configured to phase interpolate a clock signal based on the first phase interpolator control signal value to produce a phase shifted clock signal and digitally interpolate a digital sample based on the first digital interpolator signal value to produce a phase shifted digital sample having an effective phase based on the first phase control value, the digital sample generated using the phase shifted clock signal as a sample clock.

公开(公告)号：US10157637B1

公开(公告)日：2018-12-18

申请号：US15722641

申请日：2017-10-02

Applicant: Seagate Technology LLC

Inventor： Marcus Marrow ,  Jason Bellorado ,  Zheng Wu

IPC: G11B5/09 ,  G11B20/10

Abstract: Systems and methods are disclosed for sampling signals in multi-reader magnetic recording. In certain embodiments, an apparatus may comprise a plurality of read heads configured to simultaneously read from a single track of a storage medium, a plurality of analog to digital converters (ADCs) configured to receive signal patterns from corresponding read heads, and a circuit configured to control the plurality of ADCs to sample the signal patterns according to a single clock signal generator. The output of the ADCs may be individually delayed based on a down-track offset of the read heads in order to align the samples, so that samples corresponding to the same portion of the recorded signal can be combined for bit pattern detection.

公开(公告)号：US10014026B1

公开(公告)日：2018-07-03

申请号：US15713991

申请日：2017-09-25

Applicant: Seagate Technology LLC

Inventor： Zheng Wu ,  Marcus Marrow ,  Jason Bellorado

IPC: G11B20/10

CPC classification number: G11B5/59666 ,  G11B5/59633 ,  G11B20/10037 ,  G11B20/10055 ,  G11B20/10222 ,  G11B20/1024 ,  H03K5/131 ,  H03K5/135 ,  H03K2005/00019 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/091 ,  H03M1/001 ,  H03M13/2951 ,  H03M13/4146 ,  H04B1/71055 ,  H04L7/0025 ,  H04L7/0029 ,  H04L7/0331

Abstract: Systems and methods are disclosed for head delay calibration and tracking multi-sensor magnetic recording (MSMR) systems. In certain embodiments, an apparatus may comprise a first reader and a second reader configured to simultaneously read from a single track of a data storage medium, the first reader offset from the second reader such that the first reader and the second reader detect a same signal pattern offset in time. The apparatus may further comprise a circuit configured to determine a relative offset between the first reader and the second reader, including setting a fixed delay for a first signal from the first reader, setting a second delay for a second signal from the second reader, and adjusting the second delay to align the second signal to the first signal using a timing loop, with the first signal used as a reference signal.

公开(公告)号：US09819456B1

公开(公告)日：2017-11-14

申请号：US15295958

申请日：2016-10-17

Applicant: Seagate Technology LLC

Inventor： Jason Vincent Bellorado ,  Marcus Marrow

IPC: H04L1/20 ,  H04L12/801

CPC classification number: G11B20/10009 ,  H04L7/042 ,  H04L2007/047

Abstract: Systems and methods are disclosed for detection of a selected signal pattern, such as a servo sector preamble, and for frequency offset determination. A circuit may be configured to divide a signal into detection windows of a selected size, and sample the signal a selected number of times within each detection window. The circuit may then determine an error value for each detection window based on values of the samples for each detection window, and determine the preamble is detected when a threshold number of most-recently sampled detection windows have error values below a threshold value. The circuit may then organize the sample values corresponding to the preamble into groups, and calculate phase estimates representing a phase at which the groups were sampled. The circuit may determine a frequency offset based on the phase estimates, and modulate the sampling frequency according to the frequency offset.