摘要:
A signal propagation system for communicating timing information comprises a processing resource (300) arranged to generate a first timing signal for communicating the timing information, the first timing signal having a first frequency spectrum associated therewith. An electronic circuit (110) is provided having an input for receiving the timing information. An electrical connection (310) between the processing resource (300) and the electronic circuit (110) is also provided. A signal transformation module (304) for communicating the timing information, and the signal transformation module (304) is arranged to translate the first timing signal into a second timing signal for communicating the timing information. The second timing signal has a second frequency spectrum associated therewith that comprises fewer harmonics than the first timing signal, thereby reducing electromagnetic energy emitted by the electrical connection.
摘要:
The present disclosure relates to a method to determine a clock signal when separate clocks are used. In one embodiment, a disciplined clock system comprising an update subsystem and a synthesis subsystem is provided. A first clock phase estimate is provided to the update subsystem and used, along with the update subsystem, to determine a frequency offset estimate and a phase offset estimate. The clock signal is determining using the frequency offset estimate, the phase offset estimate, and the synthesis subsystem. Alternatively, two clocks can be synchronized by generating a signal associated with a first clock; modulating the signal; transmitting the modulated signal; receiving the modulated signal by a receiver associated with a second clock; correlating the received signal; determining the time of arrival of the received signal; determining the time difference between the two clocks; and synchronizing the two clocks.
摘要:
The present disclosure relates to a method to determine a clock signal when separate clocks are used. In one embodiment, a disciplined clock system comprising an update subsystem and a synthesis subsystem is provided. A first clock phase estimate is provided to the update subsystem and used, along with the update subsystem, to determine a frequency offset estimate and a phase offset estimate. The clock signal is determining using the frequency offset estimate, the phase offset estimate, and the synthesis subsystem. Alternatively, two clocks can be synchronized by generating a signal associated with a first clock; modulating the signal; transmitting the modulated signal; receiving the modulated signal by a receiver associated with a second clock; correlating the received signal; determining the time of arrival of the received signal; determining the time difference between the two clocks; and synchronizing the two clocks.
摘要:
A filter is created by sampling noise during an inter-frame gap (110) of a received signal, sampling a data frame preamble (115) from within a data frame (105) of the received signal, and computing filter coefficients based on the noise sampled during the inter-frame gap (110) and the data frame preamble (115) sampled from within the data frame (105).
摘要:
The present disclosure relates to a method to determine a clock signal when separate clocks are used. In one embodiment, a disciplined clock system comprising an update subsystem and a synthesis subsystem is provided. A first clock phase estimate is provided to the update subsystem and used, along with the update subsystem, to determine a frequency offset estimate and a phase offset estimate. The clock signal is determining using the frequency offset estimate, the phase offset estimate, and the synthesis subsystem. Alternatively, two clocks can be synchronized by generating a signal associated with a first clock; modulating the signal; transmitting the modulated signal; receiving the modulated signal by a receiver associated with a second clock; correlating the received signal; determining the time of arrival of the received signal; determining the time difference between the two clocks; and synchronizing the two clocks.
摘要:
An image data decoding method of an image vertical blanking interval (VBI) and device thereof can adjust a run-in clock signal of data lines of teletext to a data phase of teletext data lines. The method can accurately decode data of the teletext data lines to avoid a phase bias and an erroneous decoding result. A main technical method to decode the data of the VBI is to extract the data of the teletext data lines to determine corresponding bit logical values of the image data and then to output a decode result and also output a phase adjustment value. The phase adjustment value is used to adjust a read phase value of the extracted image so as to synchronize a data phase in VBI.
摘要:
The present invention discloses a host receiver synchronizer for passive optical networks, and in particular a burst clock data recovery circuit in a host receiver in a bursty asynchronous communication system having a non-data preamble of less than 250 ns, for recovering a clock signal from a subscriber data burst. The circuit comprises: an adjustable oscillator for generating an output clock signal in response to a signal at an input thereof; a first comparator for comparing a frequency and phase of the output clock signal to that of a reference signal and feeding back a first feedback signal to the oscillator input; and a second comparator for comparing the frequency and phase of the output clock signal to that of the data burst and feeding back a second feedback signal to the oscillator input once the output clock signal is locked in frequency with the reference signal. The output clock signal is locked in frequency and phase to the data burst before receipt of the last bit of the preamble. The present invention is advantageous in that the receiver circuit improves synchronized jitter performance over the prior art solutions so that additional timing margin is provided, thereby allowing longer fiber lengths to be supported.
摘要:
The present invention discloses a host receiver synchronizer for passive optical networks, and in particular a burst clock data recovery circuit in a host receiver in a bursty asynchronous communication system having a non-data preamble of less than 250 ns, for recovering a clock signal from a subscriber data burst. The circuit comprises: an adjustable oscillator for generating an output clock signal in response to a signal at an input thereof; a first comparator for comparing a frequency and phase of the output clock signal to that of a reference signal and feeding back a first feedback signal to the oscillator input; and a second comparator for comparing the frequency and phase of the output clock signal to that of the data burst and feeding back a second feedback signal to the oscillator input once the output clock signal is locked in frequency with the reference signal. The output clock signal is locked in frequency and phase to the data burst before receipt of the last bit of the preamble. The present invention is advantageous in that the receiver circuit improves synchronized jitter performance over the prior art solutions so that additional timing margin is provided, thereby allowing longer fiber lengths to be supported.
摘要:
A passive optical network comprises at least one communication facility, termed network head, coupled to at least two communication facilities, termed remote, by transmission and routing means. The network head is charged with transmitting to the remote facilities an alternation of a first portion of an optical carrier, modulated by data to be transmitted according to a chosen bit rate and lasting a first time interval, and of a second portion of this optical carrier, modulated by a clock signal at a base frequency corresponding to the bit rate and lasting a second time interval. Each remote facility is charged, on the one hand, with recovering the base frequency in the first and second received portions, and, on the other hand, with transmitting to the network head, during chosen time slots synchronized by the network head, the part which corresponds to these time slots in some at least of the second portions received successively after having overmodulated with data to be transmitted the clock signal that it contains.
摘要:
The invention provides a method and apparatus for achieving timing synchronization during signal acquisition and for achieving frequency synchronization in a digital communication receiver after signal acquisition. The invention operates by performing multiple correlations of a received signal, each correlation performed over an symbol interval and correlating the received signal in the symbol interval with a sinusoid of an expected frequency. The correlations are combined to determine a peak and energy, and if the peak to energy ratio is above a threshold, the symbol timing and frequency offset is estimated.