公开(公告)号：US07345355B2

公开(公告)日：2008-03-18

申请号：US10942607

申请日：2004-09-15

申请人： Amitabh Jain ,  Stephanie W. Butler

发明人： Amitabh Jain ,  Stephanie W. Butler

IPC分类号： H01L29/00 ,  H01L31/0288

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/1083 ,  H01L29/7833

摘要： Methods are disclosed for forming ultra shallow junctions in semiconductor substrates using multiple ion implantation steps. The ion implantation steps include implantation of at least one electronically-active dopant as well as the implantation of at least two species effective at limiting junction broadening by channeling during dopant implantation and/or by thermal diffusion. Following dopant implantation, the electronically-active dopant is activated by thermal processing.

摘要翻译： 公开了使用多个离子注入步骤在半导体衬底中形成超浅结的方法。 离子注入步骤包括植入至少一种电子活性掺杂剂以及通过在掺杂剂注入期间通过沟槽化和/或通过热扩散来有效地限制结扩展的至少两种物质的注入。 在掺杂剂注入之后，电子活性掺杂剂通过热处理而被激活。

公开(公告)号：US07344929B2

公开(公告)日：2008-03-18

申请号：US11034791

申请日：2005-01-13

申请人： Manoj Mehrotra ,  Amitabh Jain

发明人： Manoj Mehrotra ,  Amitabh Jain

IPC分类号： H01L21/00

CPC分类号： H01L21/324 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/7833

摘要： The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes forming a capping layer (210) over a transistor device having source/drain regions (150, 155) located over a substrate (110), the capping layer (210) having a degree of reflectivity, and annealing the transistor device through the capping layer (210) using photons (310), the annealing of the transistor device affected by the degree of reflectivity.

摘要翻译： 本发明提供一种制造半导体器件的方法和集成电路的制造方法。 除了其他步骤之外，制造半导体器件的方法包括在具有位于衬底（110）上方的源/漏区（150,155）的晶体管器件上形成覆盖层（210），所述覆盖层（210）具有 并且通过使用光子（310）的覆盖层（210）退火晶体管器件，晶体管器件的退火受到反射率的影响。

公开(公告)号：US20080057654A1

公开(公告)日：2008-03-06

申请号：US11469512

申请日：2006-09-01

申请人： Jihong Chen ,  Srinivasan Chakravarthi ,  Eddie H. Breashears ,  Amitabh Jain

发明人： Jihong Chen ,  Srinivasan Chakravarthi ,  Eddie H. Breashears ,  Amitabh Jain

IPC分类号： H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/6659

摘要： The present invention provides a method for manufacturing a transistor device, and a method for manufacturing an integrated circuit including the same. The method for manufacturing the transistor device, among other elements, includes forming a gate structure over a substrate, implanting an atom selected from the group consisting of fluorine, silicon, or germanium into the substrate proximate the gate structure to cause at least a portion of the substrate to be in a sub-amorphous state, and implanting a dopant into the substrate having the implanted atom therein, thereby forming source/drain regions in the substrate, wherein the transistor device does not have a halo/pocket implant.

摘要翻译： 本发明提供一种晶体管器件的制造方法及其制造方法。 制造晶体管器件的方法以及其它元件包括在衬底上形成栅极结构，将选自氟，硅或锗的原子在栅极结构附近植入到衬底中，以使至少一部分 所述衬底处于亚非晶态，并且将掺杂剂注入到其中具有注入原子的衬底中，从而在衬底中形成源极/漏极区，其中所述晶体管器件不具有卤素/穴袋注入。

公开(公告)号：US20070287274A1

公开(公告)日：2007-12-13

申请号：US11451919

申请日：2006-06-13

申请人： Mahalingam Nandakumar ,  Amitabh Jain ,  Lahir Shaik Adam

发明人： Mahalingam Nandakumar ,  Amitabh Jain ,  Lahir Shaik Adam

IPC分类号： H01L21/425

CPC分类号： H01L21/2658 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/6659 ,  H01L29/7833

摘要： Formation of an NMOS transistor is disclosed, where at least one of carbon, atomic fluorine and molecular fluorine (F2) are combined with implantations of at least one of arsenic, phosphorous and antimony. The dopant combinations can be used in LDD implantations to form source/drain extension regions, as well as in implantations to form halo regions and/or source/drain regions. The combinations of dopants help to reduce sheet resistance and increase carrier mobility, which in turn facilitates device scaling and desired device performance.

摘要翻译： 公开了一种NMOS晶体管的形成，其中碳，原子氟和分子氟（F 2 O 2）中的至少一种与砷，磷和锑中的至少一种的注入相结合。 掺杂剂组合可用于LDD注入以形成源极/漏极延伸区域，以及用于形成卤素区域和/或源极/漏极区域的注入。 掺杂剂的组合有助于降低薄层电阻并增加载流子迁移率，这进而有助于器件缩放和期望的器件性能。

公开(公告)号：US20070049022A1

公开(公告)日：2007-03-01

申请号：US11551374

申请日：2006-10-20

申请人： Peijun Chen ,  Duofeng Yue ,  Amitabh Jain ,  Sue Crank ,  Thomas Bonifield ,  Homi Mogul

发明人： Peijun Chen ,  Duofeng Yue ,  Amitabh Jain ,  Sue Crank ,  Thomas Bonifield ,  Homi Mogul

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The semiconductor device may further include source/drain regions located in/over the substrate and adjacent the gate structure, and a nickel alloy silicide located in the source/drain regions, the nickel alloy silicide having an amount of indium located therein.

摘要翻译： 本发明提供一种半导体器件，一种制造方法以及一种用于制造包括该半导体器件的集成电路的方法。 除了其他元件之外，半导体器件可以包括位于衬底上的栅极结构，栅极结构包括栅极电介质层和栅极电极层。 该半导体器件还可以包括位于衬底中或栅极结构附近的源极/漏极区域和位于源极/漏极区域中的镍合金硅化物，所述镍合金硅化物具有位于其中的铟的量。

公开(公告)号：US07163878B2

公开(公告)日：2007-01-16

申请号：US11267413

申请日：2005-11-04

申请人： Puneet Kohli ,  Mark Rodder ,  Rick Wise ,  Amitabh Jain

发明人： Puneet Kohli ,  Mark Rodder ,  Rick Wise ,  Amitabh Jain

IPC分类号： H01L21/265

CPC分类号： H01L21/26506 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： In one aspect, the present invention provides a method of forming junctions in a silicon-germanium layer (20). In this particular embodiment, the method comprises implanting a dopant (80) into the silicon-germanium layer (20) and implanting fluorine (70) into the silicon-germanium layer (20).

摘要翻译： 一方面，本发明提供一种在硅 - 锗层（20）中形成结的方法。 在该特定实施例中，该方法包括将掺杂剂（80）注入到硅 - 锗层（20）中并将氟（70）注入到硅 - 锗层（20）中。

公开(公告)号：US07118980B2

公开(公告)日：2006-10-10

申请号：US10972872

申请日：2004-10-25

申请人： Amitabh Jain

发明人： Amitabh Jain

IPC分类号： H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L21/268 ,  H01L29/6656 ,  H01L29/6659

摘要： Methods (70) are described for fabricating shallow and abrupt gradient drain extensions for MOS type transistors, in which a solid phase epitaxial recrystallization is performed within the drain extensions utilizing a laser SPER annealing process in the manufacture of semiconductor products. One method (70) includes a preamorphizing process (74) of implanting a heavy ion species such as Germanium deep into an extension region of a substrate adjacent a channel region of the substrate to form a deep amorphized region, then implanting boron or another such dopant species into an extension region of the substrate adjacent the channel region. The implanted dopant is then preannealed (78) at a low temperature to set the junction depth and doping concentration. The extensions and/or the deep source/drain regions are subsequently annealed (84) with a laser at a high temperature providing a solid phase epitaxial recrystallization in the regions proximate the channel region to achieve ultra high doping concentrations and activation levels with an abrupt gradient.

摘要翻译： 描述了用于制造用于MOS型晶体管的浅的和突然的梯度漏极延伸的方法（70），其中在半导体产品的制造中利用激光SPER退火工艺在漏极延伸内进行固相外延重结晶。 一种方法（70）包括将邻近衬底的沟道区域的衬底中的重离子物质（例如锗）深深地注入到衬底的延伸区域中以形成深非晶化区域的前变质化工艺（74），然后将硼或另一种这样的掺杂剂 物质进入邻近沟道区的衬底的延伸区域。 然后将注入的掺杂剂在低温下预退火（78）以设定结深度和掺杂浓度。 随后在高温下用激光退火延伸部分和/或深源极/漏极区域（84），从而在靠近沟道区域的区域提供固相外延重结晶，以实现超高掺杂浓度和具有突变梯度的激活水平 。

公开(公告)号：US20060154475A1

公开(公告)日：2006-07-13

申请号：US11034791

申请日：2005-01-13

申请人： Manoj Mehrotra ,  Amitabh Jain

发明人： Manoj Mehrotra ,  Amitabh Jain

IPC分类号： H01L21/4763 ,  H01L21/324

CPC分类号： H01L21/324 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/7833

摘要： The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes forming a capping layer (210) over a transistor device having source/drain regions (150, 155) located over a substrate (110), the capping layer (210) having a degree of reflectivity, and annealing the transistor device through the capping layer (210) using photons (310), the annealing of the transistor device affected by the degree of reflectivity.

摘要翻译： 本发明提供一种制造半导体器件的方法和集成电路的制造方法。 除了其他步骤之外，制造半导体器件的方法包括在具有位于衬底（110）上方的源/漏区（150,155）的晶体管器件上形成覆盖层（210），所述覆盖层（210）具有 并且通过使用光子（310）的覆盖层（210）退火晶体管器件，晶体管器件的退火受到反射率的影响。

公开(公告)号：US20050112830A1

公开(公告)日：2005-05-26

申请号：US10816776

申请日：2004-04-02

申请人： Amitabh Jain ,  Lance Robertson

发明人： Amitabh Jain ,  Lance Robertson

IPC分类号： H01L21/265 ,  H01L21/324 ,  H01L21/336

CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L21/324 ,  H01L29/6659

摘要： The invention describes a method for forming ultra shallow junction formation. Dopant species are implanted into a semiconductor. Solid phase epitaxy anneals and subsequent ultra high temperature anneals are performed following the implantation processes.

摘要翻译： 本发明描述了形成超浅结结形成的方法。 将掺杂物质注入到半导体中。 在植入过程之后进行固相外延退火和随后的超高温退火。

公开(公告)号：US06743705B2

公开(公告)日：2004-06-01

申请号：US10287979

申请日：2002-11-05

申请人： Manoj Mehrotra ,  Haowen Bu ,  Amitabh Jain

发明人： Manoj Mehrotra ,  Haowen Bu ,  Amitabh Jain

IPC分类号： H01L214763

CPC分类号： H01L29/6659 ,  H01L29/6656

摘要： A method (40) of forming an integrated circuit (60) device including a substrate (64). The method including the step of first (42), forming a gate stack (62) in a fixed relationship to the substrate, the gate stack including a gate having sidewalls. The method further includes the step of second (42), implanting source/drain extensions (701, 702) into the substrate and self-aligned relative to the gate stack. The method further includes the steps of third (46, 48), forming a first sidewall-forming layer (72) in a fixed relationship to the sidewalls and forming a second sidewall-forming layer (74) in a fixed relationship to the sidewalls. The step of forming a second sidewall-forming layer includes depositing the second sidewall-forming layer at a temperature equal to or greater than approximately 850° C. The method further includes the step of fourth (50), implanting deep source/drain regions (761, 762) into the substrate and self-aligned relative to the gate stack and the first and second sidewall-forming layers.

摘要翻译： 一种形成包括衬底（64）的集成电路（60）装置的方法（40）。 该方法包括第一步骤（42）的步骤，与衬底形成固定关系的栅叠层（62），栅叠层包括具有侧壁的栅极。 该方法还包括第二步骤（42），将源极/漏极延伸部分（701,702）注入到衬底中并相对于栅极堆叠自对准。 该方法还包括第三（46,48）的步骤，形成与侧壁成固定关系的第一侧壁形成层（72），并形成与侧壁成固定关系的第二侧壁形成层（74）。 形成第二侧壁形成层的步骤包括在等于或大于约850℃的温度下沉积第二侧壁形成层。该方法还包括第四（50）的步骤，将深源/漏区（ 761,762）插入衬底并且相对于栅极堆叠以及第一和第二侧壁形成层自对准。