公开(公告)号：US20060246645A1

公开(公告)日：2006-11-02

申请号：US11457569

申请日：2006-07-14

Applicant: Mahalingam Nandakumar ,  Seetharaman Sridhar ,  Mark Rodder

Inventor： Mahalingam Nandakumar ,  Seetharaman Sridhar ,  Mark Rodder

IPC: H01L21/8234 ,  H01L21/336

CPC classification number: H01L29/7836 ,  H01L29/6659

Abstract: A new MOS transistor is described. The transistor has a source/drain region that comprises 3 portions. Each portion is the result of a separate ion implant step. The combination of the three portions of the source/drain region yields a transistor of superior performance with high drive current, low sub-threshold current and gate-edge leakage.

Abstract translation: 描述了新的MOS晶体管。 晶体管具有包含3个部分的源极/漏极区域。 每个部分是单独的离子注入步骤的结果。 源极/漏极区域的三个部分的组合产生具有高驱动电流，低亚阈值电流和栅极边缘泄漏的优异性能的晶体管。

公开(公告)号：US20060105518A1

公开(公告)日：2006-05-18

申请号：US11267413

申请日：2005-11-04

Applicant: Puneet Kohli ,  Mark Rodder ,  Rick Wise ,  Amitabh Jain

Inventor： Puneet Kohli ,  Mark Rodder ,  Rick Wise ,  Amitabh Jain

IPC: H01L21/8238 ,  H01L21/336

CPC classification number: H01L21/26506 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: In one aspect, the present invention provides a method of forming junctions in a silicon-germanium layer (20). In this particular embodiment, the method comprises implanting a dopant (80) into the silicon-germanium layer (20) and implanting fluorine (70) into the silicon-germanium layer (20).

Abstract translation: 一方面，本发明提供一种在硅 - 锗层（20）中形成结的方法。 在该特定实施例中，该方法包括将掺杂剂（80）注入到硅 - 锗层（20）中并将氟（70）注入到硅 - 锗层（20）中。

公开(公告)号：US20050282353A1

公开(公告)日：2005-12-22

申请号：US10870020

申请日：2004-06-17

Applicant: Rick Wise ,  Mark Rodder

Inventor： Rick Wise ,  Mark Rodder

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/8238

CPC classification number: H01L21/76224 ,  H01L21/823807 ,  H01L21/823878

Abstract: The present invention provides a trench isolation structure, a method of manufacture therefor and a method for manufacturing an integrated circuit including the same. The trench isolation structure (130), in one embodiment, includes a trench located within a substrate (110), the trench having a buffer layer (133) located on sidewalls thereof. The trench isolation structure (130) further includes a barrier layer (135) located over the buffer layer (133), and fill material (138) located over the barrier layer (135) and substantially filling the trench.

Abstract translation: 本发明提供一种沟槽隔离结构及其制造方法以及包括该沟槽隔离结构的集成电路的制造方法。 在一个实施例中，沟槽隔离结构（130）包括位于衬底（110）内的沟槽，沟槽具有位于其侧壁上的缓冲层（133）。 沟槽隔离结构（130）还包括位于缓冲层（133）上的阻挡层（135）和位于阻挡层（135）上方并且基本上填充沟槽的填充材料（138）。

公开(公告)号：US20050156236A1

公开(公告)日：2005-07-21

申请号：US10979693

申请日：2004-11-01

Applicant: Mahalingam Nandakumar ,  Seetharaman Sridhar ,  Mark Rodder

Inventor： Mahalingam Nandakumar ,  Seetharaman Sridhar ,  Mark Rodder

IPC: H01L21/336 ,  H01L21/338 ,  H01L29/78 ,  H01L29/94

CPC classification number: H01L29/7836 ,  H01L29/6659

Abstract: A new MOS transistor is described. The transistor has a source/drain region that comprises 3 portions. Each portion is the result of an separate ion implant step. The combination of the three portions of the source/drain region yields a transistor of superior performance with high drive current, low sub-threshold current and gate-edge leakage.

Abstract translation: 描述了新的MOS晶体管。 晶体管具有包含3个部分的源极/漏极区域。 每个部分是单独的离子注入步骤的结果。 源极/漏极区域的三个部分的组合产生具有高驱动电流，低亚阈值电流和栅极边缘泄漏的优异性能的晶体管。

公开(公告)号：US20050280115A1

公开(公告)日：2005-12-22

申请号：US10870016

申请日：2004-06-17

Applicant: Rick Wise ,  Mark Rodder

Inventor： Rick Wise ,  Mark Rodder

IPC: H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L21/823878 ,  H01L21/76237 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present invention provides a trench isolation structure, a method of manufacture therefor and a method for manufacturing an integrated circuit including the same. The trench isolation structure (130), in one embodiment, includes a trench located within a substrate (110), the trench having an implanted buffer layer (133) located in the sidewalls thereof. The trench isolation structure (130) further includes a barrier layer (135) located over the implanted buffer layer (133), and fill material (138) located over the barrier layer (135) and substantially filling the trench.

Abstract translation: 本发明提供一种沟槽隔离结构及其制造方法以及包括该沟槽隔离结构的集成电路的制造方法。 在一个实施例中，沟槽隔离结构（130）包括位于衬底（110）内的沟槽，沟槽具有位于其侧壁中的注入缓冲层（133）。 沟槽隔离结构（130）还包括位于注入缓冲层（133）上的阻挡层（135）和位于阻挡层（135）上方并且基本上填充沟槽的填充材料（138）。

公开(公告)号：US07163878B2

公开(公告)日：2007-01-16

申请号：US11267413

申请日：2005-11-04

Applicant: Puneet Kohli ,  Mark Rodder ,  Rick Wise ,  Amitabh Jain

Inventor： Puneet Kohli ,  Mark Rodder ,  Rick Wise ,  Amitabh Jain

IPC: H01L21/265

CPC classification number: H01L21/26506 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: In one aspect, the present invention provides a method of forming junctions in a silicon-germanium layer (20). In this particular embodiment, the method comprises implanting a dopant (80) into the silicon-germanium layer (20) and implanting fluorine (70) into the silicon-germanium layer (20).

Abstract translation: 一方面，本发明提供一种在硅 - 锗层（20）中形成结的方法。 在该特定实施例中，该方法包括将掺杂剂（80）注入到硅 - 锗层（20）中并将氟（70）注入到硅 - 锗层（20）中。

公开(公告)号：US20070085164A1

公开(公告)日：2007-04-19

申请号：US11564634

申请日：2006-11-29

Applicant: Rick Wise ,  Mark Rodder

Inventor： Rick Wise ,  Mark Rodder

IPC: H01L29/00

CPC classification number: H01L21/823878 ,  H01L21/76237 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present invention provides a trench isolation structure, a method of manufacture therefor and a method for manufacturing an integrated circuit including the same. The trench isolation structure (130), in one embodiment, includes a trench located within a substrate (110), the trench having an implanted buffer layer (133) located in the sidewalls thereof. The trench isolation structure (130) further includes a barrier layer (135) located over the implanted buffer layer (133), and fill material (138) located over the barrier layer (135) and substantially filling the trench.

Abstract translation: 本发明提供一种沟槽隔离结构及其制造方法以及包括该沟槽隔离结构的集成电路的制造方法。 在一个实施例中，沟槽隔离结构（130）包括位于衬底（110）内的沟槽，沟槽具有位于其侧壁中的注入缓冲层（133）。 沟槽隔离结构（130）还包括位于注入缓冲层（133）上的阻挡层（135）和位于阻挡层（135）上方并且基本上填充沟槽的填充材料（138）。