公开(公告)号：US11316023B2

公开(公告)日：2022-04-26

申请号：US16901572

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L29/08 ,  H01L21/768 ,  H01L23/522 ,  H01L29/78

Abstract: A method includes providing two structures over a substrate and a source/drain (S/D) contact between the structures. Each structure includes a gate, two gate spacers on opposing sidewalls of the gate, and a first capping layer over the gate and the gate spacers. The method further includes recessing the S/D contact to form a trench, in which a top surface of the S/D contact is below a top surface of the gate spacers. The method further includes depositing an inhibitor layer on the S/D contact but not on surfaces of the first capping layer and not on top surfaces of the gate spacers; depositing a liner layer over top and sidewall surfaces of the first capping layer and surfaces of the gate spacers that are exposed in the trench, wherein the liner layer is free from at least a central portion of the inhibitor layer; and removing the inhibitor layer.

公开(公告)号：US20220069076A1

公开(公告)日：2022-03-03

申请号：US17159309

申请日：2021-01-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor structure includes one or more channel layers; a gate structure engaging the one or more channel layers; a first source/drain feature connected to a first side of the one or more channel layers and adjacent to the gate structure; a first dielectric cap disposed over the first source/drain feature, wherein a bottom surface of the first dielectric cap is below a top surface of the gate structure; a via disposed under and electrically connected to the first source/drain feature; and a power rail disposed under and electrically connected to the via.

公开(公告)号：US20220037192A1

公开(公告)日：2022-02-03

申请号：US17088002

申请日：2020-11-03

Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L21/768 ,  H01L21/762 ,  H01L29/66 ,  H01L23/528 ,  H01L29/417

Abstract: Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line in a direction parallel to a backside surface of the first dielectric layer.

公开(公告)号：US11239325B2

公开(公告)日：2022-02-01

申请号：US16948712

申请日：2020-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: Structures and methods that include a device such as a gate-all-around transistor formed on a frontside and a contact to one terminal of the device from the frontside of the structure and one terminal of the device from the backside of the structure. The backside contact may include selectively etching from the backside a first trench extending to expose a first source/drain structure and a second trench extending to a second source/drain structure. A conductive layer is deposited in the trenches and patterned to form a conductive via to the first source/drain structure.

公开(公告)号：US20210391431A1

公开(公告)日：2021-12-16

申请号：US16901572

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/78 ,  H01L23/522 ,  H01L21/768

Abstract: A method includes providing two structures over a substrate and a source/drain (S/D) contact between the structures. Each structure includes a gate, two gate spacers on opposing sidewalls of the gate, and a first capping layer over the gate and the gate spacers. The method further includes recessing the S/D contact to form a trench, in which a top surface of the S/D contact is below a top surface of the gate spacers. The method further includes depositing an inhibitor layer on the S/D contact but not on surfaces of the first capping layer and not on top surfaces of the gate spacers; depositing a liner layer over top and sidewall surfaces of the first capping layer and surfaces of the gate spacers that are exposed in the trench, wherein the liner layer is free from at least a central portion of the inhibitor layer; and removing the inhibitor layer.

公开(公告)号：US20210391325A1

公开(公告)日：2021-12-16

申请号：US16901963

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Li-Zhen Yu ,  Chun-Yuan Chen ,  Shih-Chuan Chiu ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L21/306 ,  H01L21/308 ,  H01L21/027

Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.

公开(公告)号：US20210384352A1

公开(公告)日：2021-12-09

申请号：US17412032

申请日：2021-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L21/02 ,  H01L27/088 ,  H01L29/66

Abstract: A method includes providing a semiconductor structure having metal gate structures (MGs), gate spacers disposed on sidewalls of the MGs, and source/drain (S/D) features disposed adjacent to the gate spacers; forming a first dielectric layer over the MGs and forming S/D contacts (MDs) over the S/D features; forming a second dielectric layer over the first dielectric layer, where portions of the second dielectric layer contact the MDs and the second dielectric layer is different from the first dielectric layer in composition; removing the portions of the second dielectric layer that contact the MDs; forming a conductive layer over the MDs and over the first dielectric layer; and removing portions of the conductive layer to form conductive features over the MDs.

公开(公告)号：US20210375758A1

公开(公告)日：2021-12-02

申请号：US16888381

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Kuan-Lun Cheng ,  Chih-Hao Wang ,  Cheng-Chi Chuang ,  Chia-Hao Chang

IPC: H01L23/528 ,  H01L21/3213 ,  H01L23/522 ,  H01L21/768

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes an active region including a channel region and a source/drain region and extending along a first direction, and a source/drain contact structure over the source/drain region. The source/drain contact structure includes a base portion extending lengthwise along a second direction perpendicular to the first direction, and a via portion over the base portion. The via portion tapers away from the base portion.

公开(公告)号：US20210375664A1

公开(公告)日：2021-12-02

申请号：US17090028

申请日：2020-11-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao Chang ,  Lin-Yu Huang ,  Li-Zhen Yu ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L21/768 ,  H01L29/417 ,  H01L23/528 ,  H01L23/532 ,  H01L21/76 ,  H01L29/40

Abstract: A method includes providing a structure having a substrate, a first dielectric layer over the substrate, one or more semiconductor channel layers over the first dielectric layer and connecting a first source/drain (S/D) feature and a second S/D feature, and a gate structure engaging the one or more semiconductor channel layers; etching the substrate from the backside of the structure to form a first trench exposing the first S/D feature and a second trench exposing the second S/D feature; forming an S/D contact in the first trench; etching at least a portion of the first dielectric layer resulting in a portion of the S/D contact protruding from the first dielectric layer at the backside of the structure; and depositing a seal layer over the S/D contact, wherein the seal layer caps an air gap between the gate structure and the seal layer.

公开(公告)号：US20210351079A1

公开(公告)日：2021-11-11

申请号：US17068037

申请日：2020-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Zhi-Chang Lin ,  Li-Zhen Yu

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: A method of forming a semiconductor transistor device. The method comprises forming a fin-shaped channel structure over a substrate and forming a first source/drain epitaxial structure and a second source/drain epitaxial structure on opposite endings of the fin structure. The method further comprises forming a metal gate structure surrounding the fin structure. The method further comprises flipping and partially removing the substrate to form a back-side capping trench while leaving a lower portion of the substrate along upper sidewalls of the first source/drain epitaxial structure and the second source/drain epitaxial structure as a protective spacer. The method further comprises forming a back-side dielectric cap in the back-side capping trench.