公开(公告)号：US20250105185A1

公开(公告)日：2025-03-27

申请号：US18402944

申请日：2024-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Ting ,  Sung-Feng Yeh ,  Ta Hao Sung ,  Gao-Long Wu ,  Shin-Jiun Fu

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: A method includes forming a function circuit on a semiconductor substrate of a device die, wherein the function circuit is in a functional circuit zone of the device die, forming a passive device over the semiconductor substrate, wherein the passive device is in a passive device zone of the device die, forming a first plurality of bond pads in the functional circuit zone and at a surface of the device die, wherein the first plurality of bond pads have a first pattern density; and forming a second plurality of bond pads in the passive device zone and at the surface of the device die. The second plurality of bond pads have a second pattern density lower than the first pattern density.

公开(公告)号：US20250105138A1

公开(公告)日：2025-03-27

申请号：US18977704

申请日：2024-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Xuan Huang ,  Hou-Yu Chen ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chung-Hui Chen

IPC: H01L23/522 ,  G11C11/22 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/528 ,  H01L23/532 ,  H01L27/12 ,  H01L27/146

Abstract: Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.

公开(公告)号：US20250105086A1

公开(公告)日：2025-03-27

申请号：US18471739

申请日：2023-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yen Lan ,  Chih-Chien Pan ,  Pu Wang ,  Li-Hui Cheng ,  Ying-Ching Shih

IPC: H01L23/367 ,  H01L23/00 ,  H01L25/16 ,  H01L25/18 ,  H10B80/00

Abstract: Various embodiments include integrated circuit packages and methods of forming integrated circuit packages. In an embodiment, a device includes: a package substrate; an integrated circuit device attached to the package substrate; a stiffener ring around the integrated circuit device and attached to the package substrate; a lid attached to the stiffener ring; a channel connected to an area between the lid and the integrated circuit device, the channel extending along at least one side of the integrated circuit device in a top-down view; and a thermal interface material in the channel and in the area between the lid and the integrated circuit device.

公开(公告)号：US20250105084A1

公开(公告)日：2025-03-27

申请号：US18530102

申请日：2023-12-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chia Lai ,  Chen-Shien Chen ,  Ting Hao Kuo ,  Jen-Yuan Chang

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: A method includes forming a dummy component, including: forming through-substrate vias (TSVs) in a substrate; forming a thermal structure over the TSVs, wherein the thermal structure includes metal lines in dielectric layers; forming a bonding layer over the thermal structure; and forming bond pads within the bonding layer; bonding the dummy component to a package component; and bonding a semiconductor die to the package component.

公开(公告)号：US20250102927A1

公开(公告)日：2025-03-27

申请号：US18472779

申请日：2023-09-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hua FU ,  Che-Chang HSU ,  Kai-Fa HO ,  Li-Jui CHEN

IPC: G03F7/00 ,  G03F7/20 ,  H01L21/027 ,  H01M8/04029 ,  H01M8/0662 ,  H01M8/24 ,  H01M10/44 ,  H01M16/00

Abstract: A method includes: forming a mask layer on a semiconductor wafer; generating light by a tin droplet by a lithography exposure system; exposing the mask layer by the light; cleaning tin debris accumulated in the lithography exposure system by hydrogen gas; pumping the hydrogen gas from the lithography exposure system to a fuel cell; and generating electric power by the fuel cell.

公开(公告)号：US20250100161A1

公开(公告)日：2025-03-27

申请号：US18974213

申请日：2024-12-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Ti WANG ,  Yi-Ming CHEN ,  Chih-Wei LIN ,  Cheng-Ho HUNG ,  Fu-Hsien LI

IPC: B25J11/00 ,  B23P6/00 ,  B25J1/04 ,  B25J18/00 ,  G01B11/24 ,  G01B11/30 ,  G01N33/00 ,  H01L21/02 ,  H01L21/66 ,  H01L21/673 ,  H01L21/677

Abstract: A method includes receiving a carrier, the carrier including a carrier body, a first filter, and a housing securing the first filter to the carrier body. The method further includes uninstalling the housing from the carrier, replacing the first filter with a second filter, reinstalling the housing on the carrier body, and inspecting the second filter. Inspecting the second filter includes using an automatic inspection mechanism to detect surface flatness of the second filter.

公开(公告)号：US12260669B2

公开(公告)日：2025-03-25

申请号：US18348460

申请日：2023-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hua Chen ,  Yu-Feng Chen ,  Chung-Shi Liu ,  Chen-Hua Yu ,  Hao-Yi Tsai ,  Yu-Chih Huang

IPC: G06V40/13 ,  H01L21/56

Abstract: A package includes a sensor die, and an encapsulating material encapsulating the sensor die therein. A top surface of the encapsulating material is substantially coplanar with or higher than a top surface of the sensor die. A plurality of sensing electrodes is higher than the sensor die and the encapsulating material. The plurality of sensing electrodes is arranged as a plurality of rows and columns, and the plurality of sensing electrodes is electrically coupled to the sensor die. A dielectric layer covers the plurality of sensing electrodes.

公开(公告)号：US20250098241A1

公开(公告)日：2025-03-20

申请号：US18962886

申请日：2024-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor process system etches gate metals on semiconductor wafers. The semiconductor process system includes a machine learning based analysis model. The analysis model dynamically selects process conditions for an atomic layer etching process. The process system then uses the selected process conditions data for the next etching process.

公开(公告)号：US20250096041A1

公开(公告)日：2025-03-20

申请号：US18955171

申请日：2024-11-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Chou ,  Su-Hao Liu ,  Kuo-Ju Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/3215 ,  H01L23/532 ,  H01L23/535 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes forming a metallic feature, forming an etch stop layer over the metallic feature, implanting the metallic feature with a dopant, forming a dielectric layer over the etch stop layer, performing a first etching process to etch the dielectric layer and the etch stop layer to form a first opening, performing a second etching process to etch the metallic feature and to form a second opening in the metallic feature, wherein the second opening is joined with the first opening, and filling the first opening and the second opening with a metallic material to form a contact plug.

公开(公告)号：US20250096008A1

公开(公告)日：2025-03-20

申请号：US18965221

申请日：2024-12-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die and a first interconnect structure coupled to the integrated circuit die. Through-vias are also coupled to the first interconnect structure. A molding material is disposed around the integrated circuit die and the through-vias over the first interconnect structure. The molding material has a pit disposed therein. A recovery material is disposed within the pit in the molding material. A second interconnect structure is disposed over the molding material, the recovery material, the integrated circuit die, and the through-vias.