公开(公告)号：US20230386911A1

公开(公告)日：2023-11-30

申请号：US18447084

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Shih-Chuan Chiu ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/321 ,  H01L23/522

CPC classification number: H01L21/7684 ,  H01L21/76802 ,  H01L21/76883 ,  H01L21/3212 ,  H01L23/5226 ,  H01L23/53209

Abstract: A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.

公开(公告)号：US20220277984A1

公开(公告)日：2022-09-01

申请号：US17745127

申请日：2022-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Shih-Chuan Chiu ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/321 ,  H01L23/522

Abstract: A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.

公开(公告)号：US20210391438A1

公开(公告)日：2021-12-16

申请号：US16901749

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chuan Chiu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Yu-Ming Lin

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/417 ,  H01L23/532 ,  H01L21/8234

Abstract: The present disclosure provides a semiconductor device structure that includes: a fin active region extruded above a semiconductor substrate; a gate stack disposed on the fin active region, wherein the gate stack includes a gate dielectric layer and a gate electrode; source/drain (S/D) features formed on the fin active region and interposed by the gate stack; and a conductive feature electrically connected to one of the gate electrode and the S/D features. The conductive feature includes a bottom metal feature of a first metal; a top metal feature of a second metal over the bottom metal feature, wherein the second metal is different from the first metal in composition; a barrier layer surrounding both the top metal feature and the bottom metal feature; and a liner surrounding both the top metal feature and separating the top metal feature from the bottom metal feature and the barrier layer.

公开(公告)号：US11018012B2

公开(公告)日：2021-05-25

申请号：US16531464

申请日：2019-08-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Li Wang ,  Yasutoshi Okuno ,  Shih-Chuan Chiu

IPC: H01L21/285 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/768 ,  H01L29/78 ,  H01L27/088

Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate, depositing a metal-rich metal silicide layer on the source/drain region, depositing a silicon-rich metal silicide layer on the metal-rich metal silicide layer, and forming a contact plug on the silicon-rich metal silicide layer. This disclosure also describes a semiconductor device including a fin structure on a substrate, a source/drain region on the fin structure, a metal-rich metal silicide layer on the source/drain region, a silicon-rich metal silicide layer on the metal-rich metal silicide layer, and a contact plug on the silicon-rich metal silicide layer.

公开(公告)号：US12266566B2

公开(公告)日：2025-04-01

申请号：US18447084

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Shih-Chuan Chiu ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin

IPC: H01L23/522 ,  H01L21/321 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.

公开(公告)号：US12027372B2

公开(公告)日：2024-07-02

申请号：US18097323

申请日：2023-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Li Wang ,  Yasutoshi Okuno ,  Shih-Chuan Chiu

IPC: H01L21/285 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/28518 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/76832 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823871 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate, depositing a metal-rich metal silicide layer on the source/drain region, depositing a silicon-rich metal silicide layer on the metal-rich metal silicide layer, and forming a contact plug on the silicon-rich metal silicide layer. This disclosure also describes a semiconductor device including a fin structure on a substrate, a source/drain region on the fin structure, a metal-rich metal silicide layer on the source/drain region, a silicon-rich metal silicide layer on the metal-rich metal silicide layer, and a contact plug on the silicon-rich metal silicide layer.

公开(公告)号：US11855144B2

公开(公告)日：2023-12-26

申请号：US17352682

申请日：2021-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chuan Chiu ,  Chia-Hao Chang ,  Jia-Chuan You ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/768

CPC classification number: H01L29/0847 ,  H01L21/76871 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device comprises a fin disposed on a substrate, a source/drain feature disposed over the fin, a silicide layer disposed over the source/drain feature, a seed metal layer disposed over the silicide layer and wrapping around the source/drain feature, and a metal layer disposed on the silicide layer, where the metal layer contacts the seed metal layer.

公开(公告)号：US20220367663A1

公开(公告)日：2022-11-17

申请号：US17814998

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chuan Chiu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Yu-Ming Lin

IPC: H01L29/49 ,  H01L29/78 ,  H01L21/8234 ,  H01L23/532 ,  H01L29/417

Abstract: The present disclosure provides a semiconductor device structure that includes: a fin active region extruded above a semiconductor substrate; a gate stack disposed on the fin active region, wherein the gate stack includes a gate dielectric layer and a gate electrode; source/drain (S/D) features formed on the fin active region and interposed by the gate stack; and a conductive feature electrically connected to the gate electrode or the S/D features. The conductive feature includes a bottom metal feature of a first metal; a top metal feature of a second metal over the bottom metal feature, wherein the second metal is different from the first metal in composition; a barrier layer surrounding both the top metal feature and the bottom metal feature; and a liner surrounding both the top metal feature and separating the top metal feature from the bottom metal feature and the barrier layer.

公开(公告)号：US20220130823A1

公开(公告)日：2022-04-28

申请号：US17572212

申请日：2022-01-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Huan-Chieh Su ,  Li-Zhen Yu ,  Chun-Yuan Chen ,  Shih-Chuan Chiu ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L21/027 ,  H01L21/308 ,  H01L21/306

Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.

公开(公告)号：US20210391325A1

公开(公告)日：2021-12-16

申请号：US16901963

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Li-Zhen Yu ,  Chun-Yuan Chen ,  Shih-Chuan Chiu ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L21/306 ,  H01L21/308 ,  H01L21/027

Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.