公开(公告)号：US20210066254A1

公开(公告)日：2021-03-04

申请号：US16903370

申请日：2020-06-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsien-Wei Chen ,  Ming-Fa Chen ,  Sung-Feng Yeh ,  Tzuan-Horng Liu

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768

Abstract: A die stack structure including a first die, an encapsulant, a redistribution layer and a second die is provided. The encapsulant laterally encapsulates the first die. The redistribution layer is disposed below the encapsulant, and electrically connected with the first die. The second die is disposed between the redistribution layer and the first die, wherein the first and second dies are electrically connected with each other, the second die comprises a body portion having a first side surface, a second side surface and a curved side surface therebetween, and the curved side surface connects the first side surface and the second side surface.

公开(公告)号：US20210066168A1

公开(公告)日：2021-03-04

申请号：US16745355

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Sung-Feng Yeh ,  Jian-Wei Hong

IPC: H01L23/48 ,  H01L23/31 ,  H01L23/544 ,  H01L21/56 ,  H01L21/768 ,  H01L21/463 ,  H01L25/065 ,  H01L25/00

Abstract: A package includes a semiconductor carrier, a first die, a second die, a first encapsulant, a second encapsulant, a first through insulating via (TIV), and a second TIV. The semiconductor carrier has a contact via embedded therein. The contact via is electrically grounded. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The second encapsulant laterally encapsulates the second die. The first TIV is aside the first die. The first TIV penetrates through the first encapsulant and is electrically connected to the contact via. The second TIV is aside the second die. The second TIV penetrates through the second encapsulant and is electrically connected to the contact via and the first TIV.

公开(公告)号：US10923421B2

公开(公告)日：2021-02-16

申请号：US16391309

申请日：2019-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Ju Chen ,  Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L21/56 ,  H01L21/768 ,  H01L25/065

Abstract: A package structure includes a semiconductor die, a redistribution circuit structure, and a connection pad. The redistribution circuit structure is located on and electrically connected to the semiconductor die. The connection pad is embedded in and electrically connected to the redistribution circuit structure, and the connection pad includes a barrier film and a conductive pattern underlying thereto, where a surface of the barrier film is substantially leveled with an outer surface of the redistribution circuit structure.

公开(公告)号：US20210020602A1

公开(公告)日：2021-01-21

申请号：US16515012

申请日：2019-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Sung-Feng Yeh ,  Tzuan-Horng Liu ,  Chao-Wen Shih

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/522 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00

Abstract: A chip structure includes first and second semiconductor chips. The first semiconductor chip includes a first semiconductor substrate, a first interconnection layer located on the first semiconductor substrate, a first protection layer covering the first interconnection layer, a gap fill layer located on the first protection layer, and first conductive vias embedded in the gap fill layer and electrically connected with the first interconnection layer. The second semiconductor chip is embedded within the first semiconductor chip and surrounded by the gap fill layer and the first conductive vias, wherein the second semiconductor chip includes a second semiconductor substrate, a second interconnection layer located on the second semiconductor substrate, a second protection layer located on the second interconnection layer, and second conductive vias embedded in the second protection layer and electrically connected with the second interconnection layer, wherein the second semiconductor substrate is bonded to the first protection layer.

公开(公告)号：US20210020601A1

公开(公告)日：2021-01-21

申请号：US16515003

申请日：2019-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen ,  Sung-Feng Yeh

IPC: H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56 ,  H01L21/02 ,  H01L25/18

Abstract: Three-dimensional integrated circuit structures and methods of forming the same are disclosed. One of the three-dimensional integrated circuit structures includes a first die, a plurality of second dies and a dielectric structure. The second dies are bonded to the first die. The dielectric structure is disposed between the second dies. The dielectric structure includes a first dielectric layer and a second dielectric layer. The first dielectric layer has a sidewall and a bottom, a first surface of the sidewall and a first surface of the bottom are in contact with the second dielectric layer and form a first angle. A second angle smaller than the first angle is formed by a second surface of the sidewall and a second surface of the bottom.

公开(公告)号：US20200381379A1

公开(公告)日：2020-12-03

申请号：US16425951

申请日：2019-05-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen ,  Ming-Fa Chen ,  Sung-Feng Yeh

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/544 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00

Abstract: Provided is a three-dimensional integrated circuit (3DIC) structure including a first die and a second die bonded together by a hybrid bonding structure. One of the first die and the second die has a pad and a cap layer disposed over the pad. The cap layer exposes a portion of a top surface of the pad, and the portion of the top surface of the pad has a probe mark. A bonding metal layer of the hybrid bonding structure penetrates the cap layer to electrically connect to the pad. A method of fabricating the first die or the second die of 3DIC structure is also provided.

公开(公告)号：US20200343183A1

公开(公告)日：2020-10-29

申请号：US16391309

申请日：2019-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Ju Chen ,  Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L21/56 ,  H01L21/768 ,  H01L25/065

Abstract: A package structure includes a semiconductor die, a redistribution circuit structure, and a connection pad. The redistribution circuit structure is located on and electrically connected to the semiconductor die. The connection pad is embedded in and electrically connected to the redistribution circuit structure, and the connection pad includes a barrier film and a conductive pattern underlying thereto, where a surface of the barrier film is substantially levelled with an outer surface of the redistribution circuit structure.

公开(公告)号：US10811390B2

公开(公告)日：2020-10-20

申请号：US16252727

申请日：2019-01-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L21/66 ,  H01L21/768 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

Abstract: Provided is a die stack structure including a first die and a second die. The first die and the second die are bonded together through a hybrid bonding structure. A bonding insulating layer of the hybrid bonding structure extends to contact with one interconnect structure of the first die or the second die.

公开(公告)号：US20200328200A1

公开(公告)日：2020-10-15

申请号：US16915064

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chen-Hua Yu

IPC: H01L25/00 ,  H01L21/48 ,  H01L23/00 ,  H01L21/768 ,  H01L23/538 ,  H01L23/522 ,  H01L25/07

Abstract: Semiconductor devices are provided in which a first semiconductor device is bonded to a second semiconductor device. The bonding may occur at a gate level, a gate contact level, a first metallization layer, a middle metallization layer, or a top metallization layer of either the first semiconductor device or the second semiconductor device.

公开(公告)号：US20200312758A1

公开(公告)日：2020-10-01

申请号：US16901330

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Sung-Feng Yeh ,  Ming-Fa Chen ,  Hsien-Wei Chen

IPC: H01L23/498 ,  H01L25/10 ,  H01L25/00 ,  H01L21/683 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00

Abstract: A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, forming stacked vias in the plurality of dielectric layers with the stacked vias forming a continuous electrical connection penetrating through the plurality of dielectric layers, forming a dielectric layer over the stacked vias and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, and bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding.