公开(公告)号：US11469109B2

公开(公告)日：2022-10-11

申请号：US16353531

申请日：2019-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Ziwei Fang

IPC: H01L21/285 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/08 ,  H01L29/45

Abstract: A semiconductor structure having metal contact features and a method for forming the same are provided. The method includes forming a dielectric layer covering an epitaxial structure over a semiconductor substrate and forming an opening in the dielectric layer to expose the epitaxial structure. The method includes forming a metal-containing layer over the dielectric layer and the epitaxial structure. The method includes heating the epitaxial structure and the metal-containing layer to transform a first portion of the metal-containing layer contacting the epitaxial structure into a metal-semiconductor compound layer. The method includes oxidizing the metal-containing layer to transform a second portion of the metal-containing layer over the metal-semiconductor compound layer into a metal oxide layer. The method includes applying a metal chloride-containing etching gas on the metal oxide layer to remove the metal oxide layer and forming a metal contact feature over the metal-semiconductor compound layer.

公开(公告)号：US11282940B2

公开(公告)日：2022-03-22

申请号：US16946736

申请日：2020-07-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming Lin ,  Kai Tak Lam ,  Sai-Hooi Yeong ,  Chi On Chui ,  Ziwei Fang

IPC: H01L29/00 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L21/768

Abstract: A semiconductor structure that includes a semiconductor fin disposed over a substrate, S/D features disposed over the semiconductor fin, and a metal gate stack interposed between the S/D features. The metal gate stack includes a gate dielectric layer disposed over the semiconductor fin, a capping layer disposed over the gate dielectric layer, and a gate electrode disposed over the capping layer, where the gate dielectric layer includes hafnium oxide with hafnium atoms and oxygen atoms arranged in a Pca21 space group.

公开(公告)号：US11195938B2

公开(公告)日：2021-12-07

申请号：US16526650

申请日：2019-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING , CO., LTD.

Inventor： Cheng-Ming Lin ,  Sai-Hooi Yeong ,  Chi-On Chui ,  Ziwei Fang

IPC: G11C11/22 ,  H01L21/28 ,  H01L27/1159 ,  H01L29/78 ,  H01L21/283 ,  H01L21/3205 ,  H01L29/06 ,  H01L29/66 ,  H01L29/51 ,  H01L21/02 ,  H01L29/423

Abstract: A method for forming a semiconductor structure is provided. The method includes patterning a semiconductor substrate to form a semiconductor fin, forming a source/drain structure on the semiconductor fin, forming an interfacial layer on the semiconductor fin, treating the interfacial layer with fluorine, forming a ferroelectric gate dielectric layer on the interfacial layer, treating the ferroelectric gate dielectric layer with fluorine, and forming a gate electrode layer on the ferroelectric gate dielectric layer.

公开(公告)号：US11195931B2

公开(公告)日：2021-12-07

申请号：US16994865

申请日：2020-08-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hsiung Tsai ,  Kuo-Feng Yu ,  Chien-Tai Chan ,  Ziwei Fang ,  Kei-Wei Chen ,  Huai-Tei Yang

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L21/225

Abstract: A gate structure, a semiconductor device, and the method of forming a semiconductor device are provided. In various embodiments, the gate structure includes a gate stack and a doped spacer overlying a sidewall of the gate stack. The gate stack contains a doped work function metal (WFM) stack and a metal gate electrode overlying the doped WFM stack.

公开(公告)号：US20210351278A1

公开(公告)日：2021-11-11

申请号：US17228415

申请日：2021-04-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ming LIN ,  Sai-Hooi Yeong ,  Ziwei Fang ,  Chi On Chui ,  Huang-Lin Chao

IPC: H01L29/51 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L27/088

Abstract: The present disclosure describes a device that is protected from the effects of an oxide on the metal gate layers of ferroelectric field effect transistors. In some embodiments, the device includes a substrate with fins thereon; an interfacial layer on the fins; a crystallized ferroelectric layer on the interfacial layer; and a metal gate layer on the ferroelectric layer.

公开(公告)号：US11139397B2

公开(公告)日：2021-10-05

申请号：US16572255

申请日：2019-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming Lin ,  Sai-Hooi Yeong ,  Ziwei Fang ,  Chi On Chui ,  Huang-Lin Chao

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/66

Abstract: The present disclosure relates to methods for forming a semiconductor device. The method includes forming a substrate and forming first and second spacers on the substrate. The method includes depositing first and second self-assembly (SAM) layers respectively on sidewalls of the first and second spacers and depositing a layer stack on the substrate and between and in contact with the first and second SAM layers. Depositing the layer stack includes depositing a ferroelectric layer and removing the first and second SAM layers. The method further includes depositing a metal compound layer on the ferroelectric layer. Portions of the metal compound layer are deposited between the ferroelectric layer and the first or second spacers. The method also includes depositing a gate electrode on the metal compound layer and between the first and second spacers.

公开(公告)号：US20210225644A1

公开(公告)日：2021-07-22

申请号：US16745532

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Christine Y. OUYANG ,  Ziwei Fang

IPC: H01L21/02 ,  C23C16/02 ,  C23C16/455 ,  H01L21/768

Abstract: The present disclosure relates to a method of fabricating a semiconductor structure, the method includes forming an opening and depositing a metal layer in the opening. The depositing includes performing one or more deposition cycles, wherein each deposition cycle includes flowing a first precursor into a deposition chamber and performing an ultraviolet (UV) radiation process on the first precursor. The method further includes performing a first purging process in the deposition chamber to remove at least a portion of the first precursor, flowing a second precursor into the deposition chamber, and purging the deposition chamber to remove at least a portion of the second precursor.

公开(公告)号：US11031490B2

公开(公告)日：2021-06-08

申请号：US16454854

申请日：2019-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming Lin ,  Sai-Hooi Yeong ,  Chi On Chui ,  Ziwei Fang ,  Huang-Lin Chao

IPC: H01L29/66 ,  H01L29/51 ,  H01L21/02

Abstract: A method of forming a semiconductor device includes forming a sacrificial layer on sidewalls of gate spacers disposed over a semiconductor layer, forming a first hafnium-containing gate dielectric layer over the semiconductor layer in a first trench disposed between the gate spacers, removing the sacrificial layer to form a second trench between the gate spacers and the first hafnium-containing gate dielectric layer, forming a second hafnium-containing gate dielectric layer over the first hafnium-containing gate dielectric layer and on the sidewalls of the gate spacers, annealing the first and the second hafnium-containing gate dielectric layers while simultaneously applying an electric field, and subsequently forming a gate electrode over the annealed first and second hafnium-containing gate dielectric layers.

公开(公告)号：US11018256B2

公开(公告)日：2021-05-25

申请号：US16549245

申请日：2019-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming Lin ,  Sai-Hooi Yeong ,  Ziwei Fang ,  Chi On Chui ,  Huang-Lin Chao

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02

Abstract: The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.

公开(公告)号：US10985265B2

公开(公告)日：2021-04-20

申请号：US16548446

申请日：2019-08-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Liang Cheng ,  I-Ming Chang ,  Hsiang-Pi Chang ,  Hsueh-Wen Tsau ,  Ziwei Fang ,  Huang-Lin Chao

IPC: H01L29/66 ,  H01L29/78

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a semiconductor layer on a semiconductor substrate, forming an interfacial layer on the semiconductor layer, forming a first gate dielectric layer on the interfacial layer, introducing fluorine on the first gate dielectric layer, annealing the first gate dielectric layer, forming a second gate dielectric layer on the first gate dielectric layer, introducing fluorine on the second gate dielectric layer, annealing the second gate dielectric layer, and forming a gate stack structure on the second gate dielectric layer.