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116 条记录 (耗时 0.037 秒)

    Silver halide color photographic light-sensitive material in roll form
    61.
    发明授权
    Silver halide color photographic light-sensitive material in roll form 失效
    卤化银彩色照相感光材料卷状

    公开(公告)号：US5312725A

    公开(公告)日：1994-05-17

    申请号：US41683

    申请日：1993-04-01

    申请人： Hiromitsu Araki ,  Tohru Kobayashi ,  Eiichi Ueda

    发明人： Hiromitsu Araki ,  Tohru Kobayashi ,  Eiichi Ueda

    IPC分类号： G03C1/76 ,  G03C1/81

    CPC分类号： G03C1/7614 ,  G03C1/81 ,  Y10S430/131

    摘要： A silver halide color photographic light-sensitive material in roll form comprises a support, and provided thereon, a silver halide emulsion layer and, on the side of the support opposite the silver halide emulsion layer, a backing layer containing gelatin and a hardener, wherein the backing layer has a degree of swelling of 250% or less represented by the following equation:Degree of swelling=[(A-C)/(B-C)].times.100.

    摘要翻译： 卷状的卤化银彩色照相感光材料包括载体，并且在其上提供卤化银乳剂层，并且在与卤化银乳剂层相对的载体侧面上含有明胶和硬化剂的背衬层，其中 背衬层具有以下等式表示的250％以下的溶胀度：溶胀度= [（AC）/（BC）]×100。

    Semiconductor integrated circuit device with a plurality of logic circuits having active pull-down functions
    62.
    发明授权
    Semiconductor integrated circuit device with a plurality of logic circuits having active pull-down functions 失效
    具有多个具有主动下拉功能的逻辑电路的半导体集成电路器件

    公开(公告)号：US5298802A

    公开(公告)日：1994-03-29

    申请号：US56798

    申请日：1993-05-03

    申请人： Mitsuo Usami ,  Noboru Shiozawa ,  Toshio Yamada ,  Hiromasa Katoh ,  Kazuyoshi Satoh ,  Tohru Kobayashi ,  Tatsuya Kimura ,  Masato Hamamoto ,  Atsushi Shimizu ,  Kaoru Koyu

    发明人： Mitsuo Usami ,  Noboru Shiozawa ,  Toshio Yamada ,  Hiromasa Katoh ,  Kazuyoshi Satoh ,  Tohru Kobayashi ,  Tatsuya Kimura ,  Masato Hamamoto ,  Atsushi Shimizu ,  Kaoru Koyu

    IPC分类号： H03K3/2885 ,  H03K17/0412 ,  H03K17/66 ,  H03K19/013 ,  H03K19/086

    CPC分类号： H03K19/086 ,  H03K17/04126 ,  H03K17/666 ,  H03K19/0136 ,  H03K3/2885

    摘要： In accordance with one aspect of the invention, a semiconductor integrated circuit is provided wherein an input circuit is formed by a phase split circuit having a bipolar transistor which outputs an inverted output from the collector and a non-inverted output from the emitter. The emitter follower output circuit is driven by an inverted output of the phase split circuit. Meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit. As a second aspect of the invention, a logic circuit is formed of a logic portion and an output portion. The output portion includes an emitter follower output transistor receiving an output signal generated by the logic portion and an active pull-down transistor receiving at its base a signal supplied thereto through a capacitance element. The signal received by the active pull-down transistor has a phase reverse to that of the input signal supplied to the base of said output transistor. Between the base and emitter of the active pull-down transistor, there is disposed a bias circuit formed of a transistor receiving at its base a predetermined bias voltage and an emitter resistor. Further, between a junction point of the emitter follower output transistor and the active pull-down transistor and the emitter of the transistor as a constituent of the bias circuit, there is disposed a capacitance element for feeding back the output signal.

    摘要翻译： 根据本发明的一个方面，提供一种半导体集成电路，其中输入电路由具有从集电极输出反相输出的双极晶体管和来自发射极的非反相输出的相位分离电路形成。 射极跟随器输出电路由相位分离电路的反相输出驱动。 同时，射极跟随器输出电路的发射极负载由晶体管形成，并且发射极负载晶体管由相分离的非反相输出的上升沿的待充电电容的充电电流导通地临时驱动 电路。 作为本发明的第二方面，逻辑电路由逻辑部分和输出部分组成。 输出部分包括接收由逻辑部分产生的输出信号的射极跟随器输出晶体管和有源下拉晶体管，在其底部接收通过电容元件提供给它的信号。 由有源下拉晶体管接收的信号与提供给所述输出晶体管的基极的输入信号的相位相反。 在有源下拉晶体管的基极和发射极之间设置偏置电路，该偏置电路由其基极接收预定偏置电压的晶体管和发射极电阻构成。 此外，在射极跟随器输出晶体管的连接点和有源下拉晶体管和作为偏置电路的组成部分的晶体管的发射极之间，设置有用于反馈输出信号的电容元件。

    Method of making photographic element having epoxy overlayer
    66.
    发明授权
    Method of making photographic element having epoxy overlayer 失效
    制造具有环氧树脂覆层的照相元件的方法

    公开(公告)号：US5178996A

    公开(公告)日：1993-01-12

    申请号：US897578

    申请日：1992-06-11

    申请人： Tohru Kobayashi ,  Yasuo Nishi ,  Nakaya Nakano ,  Kazuo Ohkawa ,  Hiroyuki Tachikawa

    发明人： Tohru Kobayashi ,  Yasuo Nishi ,  Nakaya Nakano ,  Kazuo Ohkawa ,  Hiroyuki Tachikawa

    IPC分类号： G03C11/08

    CPC分类号： G03C11/08 ,  Y10S430/162

    摘要： Disclosed is a photographic element having a support, at least one layer for carrying an image on the support and a protective coated layer cured by an active energy ray thereon, wherein the protective coated layer is one obtained by curing, by irradiation of an active energy ray, an active energy ray curable composition containing a prepolymer containing at least 2 epoxy groups in the molecule and a polymerization initiator which can be activated by the active energy ray; and the active energy ray curable composition is coated on the layer carrying the image; and the layer carrying the image has a water content of 20.0% by weight or less. Disclosed is also a process for preparing the photographic element constituted as the above.

    摘要翻译： 公开了一种具有支撑体的照相元件，用于在支撑体上承载图像的至少一层和通过其上的活性能量射线固化的保护涂层，其中保护涂层是通过照射活性能量 ray，一种活性能量射线固化性组合物，其含有在分子中含有至少2个环氧基的预聚物和可以通过活性能量射线活化的聚合引发剂; 并且将活性能量射线固化性组合物涂布在承载图像的层上; 携带图像的层的含水量为20.0重量％以下。 还公开了制备如上所述的照相材料的方法。

    Integrated logic circuit
    67.
    发明授权
    Integrated logic circuit 失效
    集成逻辑电路

    公开(公告)号：US5059819A

    公开(公告)日：1991-10-22

    申请号：US133915

    申请日：1987-12-16

    申请人： Kazuo Tanaka ,  Masato Hamamoto ,  Toshio Yamada ,  Tohru Kobayashi ,  Hiromasa Katoh

    发明人： Kazuo Tanaka ,  Masato Hamamoto ,  Toshio Yamada ,  Tohru Kobayashi ,  Hiromasa Katoh

    IPC分类号： G01R31/3185 ,  H01L27/02

    CPC分类号： H01L27/0207 ,  G01R31/318538 ,  G01R31/318572

    摘要： Flip-flops are disposed corresponding to input circuits or output circuits of an integrated logic circuit so as to be cascaded to configure a shift register for a test and to enable a parallel transfer of data between each flip-flop and a corresponding input or output circuit. As a result, without connecting the probe to all terminals of the LSI, test signals can be supplied from some terminals via all input circuits to an internal circuit so as to conduct a diagnosis.

    摘要翻译： 触发器对应于集成逻辑电路的输入电路或输出电路进行布置，以便级联以配置用于测试的移位寄存器，并且能够在每个触发器和相应的输入或输出电路之间并行传输数据 。 结果，在不将探头连接到LSI的所有端子的情况下，可以通过所有输入电路从一些端子向内部电路提供测试信号，以进行诊断。

    Semiconductor integrated circuit device having an improved common wiring arrangement
    68.
    发明授权
    Semiconductor integrated circuit device having an improved common wiring arrangement 失效
    具有改进的公共布线布置的半导体集成电路器件

    公开(公告)号：US4987326A

    公开(公告)日：1991-01-22

    申请号：US344669

    申请日：1989-04-28

    申请人： Yasuo Satoh ,  Tohru Kobayashi

    发明人： Yasuo Satoh ,  Tohru Kobayashi

    IPC分类号： H01L21/82 ,  H01L23/528 ,  H01L27/118 ,  H03K19/173

    CPC分类号： H03K19/1735 ,  H01L23/528 ,  H01L27/11801 ,  H01L2924/0002

    摘要： In a gate array integrated circuit including a plurality of logic gate circuits having a wired-OR form, or the like, a first common combined wiring is provided for connecting the output side in such a manner that the output terminal of each logic gate circuit and a branch node corresponding thereto are in the proximity of one another. A terminal resistor is interposed between a first end of the first common combined wiring and a power source voltage or ground potential of the circuit, and the second end of the first common combined wiring is coupled to a second common combined wiring connecting the input terminals of the logic gate circuits on the input side.

    摘要翻译： 在包括多个逻辑门电路的门阵列集成电路中，具有布线或形式等，提供第一公共组合布线，用于连接输出侧，使得每个逻辑门电路的输出端和 与之对应的分支节点彼此靠近。 终端电阻器插入在第一公共组合布线的第一端和电路的电源电压或地电位之间，第一公共组合布线的第二端耦合到第二公共组合布线，第二公共组合布线将 输入侧的逻辑门电路。

    ECL Circuit having a negative feedback differential transistor circuit to increase the operating speed of the output circuit
    70.
    发明授权
    ECL Circuit having a negative feedback differential transistor circuit to increase the operating speed of the output circuit 失效
    ECL电路具有负反馈差分晶体管电路，以增加输出电路的工作速度

    公开(公告)号：US4563600A

    公开(公告)日：1986-01-07

    申请号：US441180

    申请日：1982-11-12

    申请人： Tohru Kobayashi ,  Kazuo Nakamura

    发明人： Tohru Kobayashi ,  Kazuo Nakamura

    IPC分类号： H03K19/013 ,  H03K19/018 ,  H03K19/086 ,  H03K19/092

    CPC分类号： H03K19/01812 ,  H03K19/013 ,  H03K19/086

    摘要： An ECL semiconductor integrated circuit is constructed of an input circuit, a minor amplitude ECL circuit and an output circuit. The input circuit has its operating speed improved by using a negative feedback type differential transistor circuit. Thanks to the improvement in the operating speed of the input circuit, the overall response time of the ECL semiconductor integrated circuit can be significantly shortened. The output circuit is arranged to operate in conjunction with a minor amplitude signal received from the ECL circuit, and can include provisions both for generating minor level signals for the ECL and an output circuit at a normal ECL level for coupling to external circuit operating at such a normal level. Also, in one embodiment, the output circuit can operate with a negative feedback type differential transistor circuit to increase the operating speed of the output circuit.

    摘要翻译： ECL半导体集成电路由输入电路，次振幅ECL电路和输出电路构成。 通过使用负反馈型差分晶体管电路，输入电路的工作速度得到改善。 由于输入电路的运行速度有所改善，ECL半导体集成电路的整体响应时间可以大大缩短。 输出电路被配置为与从ECL电路接收的次振幅信号一起工作，并且可以包括用于为ECL生成次级信号和在正常ECL电平处的输出电路的装置，用于耦合到在这样操作的外部电路 正常水平 此外，在一个实施例中，输出电路可以利用负反馈型差分晶体管电路工作，以增加输出电路的工作速度。