公开(公告)号：US20070111410A1

公开(公告)日：2007-05-17

申请号：US11622169

申请日：2007-01-11

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/78603

摘要： An integrated circuit structure has a buried oxide (BOX) layer above a substrate, and a first-type fin-type field effect transistor (FinFET) and a second-type FinFET above the BOX layer. The second region of the BOX layer includes a seed opening to the substrate. The top of the first-type FinFET and the second-type FinFET are planar with each other. A first region of the BOX layer below the first FinFET fin is thicker above the substrate when compared to a second region of the BOX layer below the second FinFET fin. Also, the second FinFET fin is taller than the first FinFET fin. The height difference between the first fin and the second fin permits the first-type FinFET to have the same drive strength as the second-type FinFET.

摘要翻译： 集成电路结构在衬底上方具有掩埋氧化物（BOX）层，以及在BOX层上方的第一型鳍型场效应晶体管（FinFET）和第二类型FinFET。 BOX层的第二区域包括到基板的种子开口。 第一型FinFET和第二型FinFET的顶部彼此平坦。 当与第二FinFET鳍片下面的BOX层的第二区域相比时，第一FinFET鳍片下面的BOX层的第一区域比衬底上方更厚。 此外，第二个FinFET鳍片比第一个FinFET鳍片高。 第一鳍片和第二鳍片之间的高度差允许第一类型的FinFET具有与第二类型FinFET相同的驱动强度。

公开(公告)号：US20070102747A1

公开(公告)日：2007-05-10

申请号：US11164109

申请日：2005-11-10

申请人： Jia Chen ,  Edward Nowak

发明人： Jia Chen ,  Edward Nowak

IPC分类号： H01L29/76

CPC分类号： H01L51/055 ,  B82Y10/00 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0558 ,  Y10S977/742 ,  Y10S977/94

摘要： Disclosed is a CNT technology that overcomes the intrinsic ambipolar properties of CNTFETs. One embodiment of the invention provides either a stable p-type CNTFET or a stable n-type CNTFET. Another embodiment of the invention provides a complementary CNT device. In order to overcome the ambipolar properties of a CNTFET, source/drain gates are introduced below the CNT opposite the source/drain electrodes. These source/drain gates are used to apply either a positive or negative voltage to the ends of the CNT so as to configure the corresponding FET as either an n-type or p-type CNTFET, respectively. Two adjacent CNTFETs, configured such that one is an n-type CNTFET and the other is a p-type CNTFET, can be incorporated into a complementary CNT device. In order to independently adjust threshold voltage of an individual CNTFET, a back gate can also be introduced below the CNT and, particularly, below the channel region of the CNT opposite the front gate. In this manner parasitic capacitances and resistances are minimized.

摘要翻译： 公开了克服CNTFET的固有双极性能的CNT技术。 本发明的一个实施例提供稳定的p型CNTFET或稳定的n型CNTFET。 本发明的另一实施例提供了一种互补的CNT器件。 为了克服CNTFET的双极性质，源极/漏极栅极被引入到与源极/漏极电极相对的CNT之下。 这些源极/漏极栅极用于向CNT的端部施加正或负电压，以将相应的FET分别构造为n型或p型CNTFET。 可以将两个相邻的CNTFET配置成互补CNT器件，其被配置为使得一个是n型CNTFET，另一个是p型CNTFET。 为了独立地调节各个CNTFET的阈值电压，也可以在CNT下面，特别是在与前栅极相对的CNT的沟道区下方引入背栅。 以这种方式，寄生电容和电阻最小化。

公开(公告)号：US20070063276A1

公开(公告)日：2007-03-22

申请号：US11162663

申请日：2005-09-19

申请人： Jochen Beintner ,  Thomas Ludwig ,  Edward Nowak

发明人： Jochen Beintner ,  Thomas Ludwig ,  Edward Nowak

IPC分类号： H01L27/12 ,  H01L21/20

CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

摘要： A method, structure and alignment procedure, for forming a finFET. The method including, defining a first fin of the finFET with a first mask and defining a second fin of the finFET with a second mask. The structure including integral first and second fins of single-crystal semiconductor material and longitudinal axes of the first and second fins aligned in the same crystal direction but offset from each other. The alignment procedure including simultaneously aligning alignment marks on a gate mask to alignment targets formed separately by a first masked used to define the first fin and a second mask used to define the second fin.

摘要翻译： 用于形成finFET的方法，结构和取向程序。 该方法包括：用第一掩模限定finFET的第一鳍片，并用第二掩模限定finFET的第二鳍片。 该结构包括单晶半导体材料的整体第一和第二鳍片以及第一和第二鳍片的纵向轴线在相同的晶体方向上排列但彼此偏移。 对准过程包括同时将栅极掩模上的对准标记对准由通过用于限定第一鳍片的第一掩模单独形成的对准靶和用于限定第二鳍片的第二掩模。

公开(公告)号：US20070010049A1

公开(公告)日：2007-01-11

申请号：US11160360

申请日：2005-06-21

申请人： Brent Anderson ,  Edward Nowak ,  Jed Rankin ,  William Clark

发明人： Brent Anderson ,  Edward Nowak ,  Jed Rankin ,  William Clark

IPC分类号： H01L21/8234

CPC分类号： H01L29/78606 ,  H01L27/0248 ,  H01L29/42384 ,  H01L29/785

摘要： A fin-type field effect transistor has an insulator layer above a substrate and a fin extending above the insulator layer. The fin has a channel region, and source and drain regions. A gate conductor is positioned over the channel region. The insulator layer includes a heat dissipating structural feature adjacent the fin, and a portion of the gate conductor contacts the heat dissipating structural feature. The heat dissipating structural feature can comprise a recess within the insulator layer or a thermal conductor extending through the insulator layer.

公开(公告)号：US20060292772A1

公开(公告)日：2006-12-28

申请号：US11160457

申请日：2005-06-24

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L21/8234 ,  H01L21/336 ,  H01L21/84

CPC分类号： H01L21/823437 ,  H01L21/823412 ,  H01L21/84 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/78609 ,  Y10S257/903

摘要： Disclosed is a method of forming a pair of transistors by epitaxially growing a pair of silicon fins on a silicon germanium fin on a bulk wafer. In one embodiment a gate conductor between the fins is isolated from a conductor layer on the bulk wafer so a front gate may be formed. In another embodiment a gate conductor between the fins contacts a conductor layer on the bulk wafer so a back gate may be formed. In yet another embodiment both of the previous structures are simultaneously formed on the same bulk wafer. The method allow the pairs of transistors to be formed with a variety of features (e.g., strained fins, a space between two fins that is approximately 0.5 to 3 times greater than a width of a single fin, a first dielectric layer on the inner sidewalls of each pair of fins with a different thickness and/or a different dielectric material than a second dielectric layer on the outer sidewalls of each pair of fins, etc.).

摘要翻译： 公开了通过在体晶片上的硅锗翅片上外延生长一对硅散热片来形成一对晶体管的方法。 在一个实施例中，翅片之间的栅极导体与体晶片上的导体层隔离，因此可以形成前栅极。 在另一个实施例中，翅片之间的栅极导体接触体晶片上的导体层，因此可形成背栅。 在另一个实施例中，两个先前的结构同时形成在相同的体晶片上。 该方法允许成对的晶体管形成有各种特征（例如，应变翅片，两个翅片之间的空间，比单个鳍片的宽度大约0.5至3倍，内侧壁上的第一介电层 每个翅片具有与每对翅片的外侧壁上的第二介电层不同的厚度和/或不同的电介质材料等）。

公开(公告)号：US20060286724A1

公开(公告)日：2006-12-21

申请号：US11160361

申请日：2005-06-21

申请人： Brent Anderson ,  Matthew Breitwisch ,  Edward Nowak

发明人： Brent Anderson ,  Matthew Breitwisch ,  Edward Nowak

IPC分类号： H01L21/84 ,  H01L29/76

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

摘要： Disclosed is a tri-gate field effect transistor with a back gate and the associated methods of forming the transistor. Specifically, a back gate is incorporated into a lower portion of a fin. A tri-gate structure is formed on the fin and is electrically isolated from the back gate. The back gate can be used to control the threshold voltage of the FET. In one embodiment the back gate extends to an n-well in a p-type silicon substrate. A contact to the n-well allows electrical voltage to be applied to the back gate. A diode created between the n-well and p-substrate isolates the current flowing through the n-well from other devices on the substrate so that the back gate can be independently biased. In another embodiment the back gate extends to n-type polysilicon layer on an insulator layer on a p-type silicon substrate. A contact to the n-type polysilicon layer allows electrical voltage to be applied to the back gate. A trench isolation structure extending through the polysilicon layer to the insulator layer isolates current flowing through the polysilicon layer from other devices on the silicon substrate.

摘要翻译： 公开了具有背栅的三栅场效应晶体管和形成晶体管的相关方法。 具体地说，后门结合在翅片的下部。 三栅结构形成在翅片上并与后门电隔离。 背栅可用于控制FET的阈值电压。 在一个实施例中，背栅极延伸到p型硅衬底中的n阱。 与n阱的接触允许将电压施加到后门。 在n阱和p衬底之间产生的二极管将流过n阱的电流与衬底上的其他器件隔离，使得后栅极可以被独立地偏置。 在另一个实施例中，背栅极延伸到p型硅衬底上的绝缘体层上的n型多晶硅层。 与n型多晶硅层的接触允许电压施加到后门。 通过多晶硅层延伸到绝缘体层的沟槽隔离结构将流过多晶硅层的电流与硅衬底上的其它器件隔离。

公开(公告)号：US20060244062A1

公开(公告)日：2006-11-02

申请号：US10908117

申请日：2005-04-28

申请人： William Clark ,  Edward Nowak

发明人： William Clark ,  Edward Nowak

IPC分类号： H01L27/12

CPC分类号： H01L29/78648

摘要： Structures and a method for detecting ionizing radiation using silicon-on-insulator (SOI) technology are disclosed. In one embodiment, the invention includes a substrate having a buried insulator layer formed over the substrate and an active layer formed over the buried insulator layer. Active layer may be fully depleted. A transistor is formed over the active layer, and includes a first gate conductor, a first gate dielectric and source/drain diffusion regions. The first gate conductor may include a material having a substantially (or fully) depleted doping concentration such that it has a resistivity higher than doped polysilicon such as intrinsic polysilicon. A second gate conductor is formed below the buried insulator layer and provides a second gate dielectric corresponding to the second gate conductor. A channel region between the first gate conductor and the second gate conductor is controlled by the second gate conductor (back gate) such that it acts as a radiation detector.

摘要翻译： 公开了使用绝缘体上硅（SOI）技术检测电离辐射的结构和方法。 在一个实施例中，本发明包括具有在衬底上形成的掩埋绝缘体层的衬底和形成在掩埋绝缘体层上的有源层。 活性层可能完全耗尽。 在有源层上形成晶体管，并且包括第一栅极导体，第一栅极电介质和源极/漏极扩散区。 第一栅极导体可以包括具有基本（或完全）耗尽的掺杂浓度的材料，使得其具有比诸如本征多晶硅的掺杂多晶硅更高的电阻率。 第二栅极导体形成在掩埋绝缘体层下方，并提供对应于第二栅极导体的第二栅极电介质。 第一栅极导体和第二栅极导体之间​​的沟道区域由第二栅极导体（背栅极）控制，使得其作为辐射检测器。

公开(公告)号：US20060228862A1

公开(公告)日：2006-10-12

申请号：US10907568

申请日：2005-04-06

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L21/00

CPC分类号： H01L21/823425 ,  H01L21/823475 ,  H01L27/0207 ,  H01L29/78 ,  H01L29/7851 ,  H01L2029/7858

摘要： A complementary metal oxide semiconductor field effect transistor (CMOS FET) design layout and method of fabrication are disclosed that provide a long gate and dense pitch in which gate contacts are positioned directly on top of the gates, and source and drain contacts are made into contact CA bars with contact pads outside the RX (active silicon conductor) region of the FET.

摘要翻译： 公开了互补金属氧化物半导体场效应晶体管（CMOS FET）的制造布局和制造方法，其提供了长栅极和密集间距，其中栅极触点直接位于栅极的顶部，并且源极和漏极触点被形成接触 CA焊条在FET的RX（有源硅导体）区域外部具有接触焊盘。

公开(公告)号：US20060183289A1

公开(公告)日：2006-08-17

申请号：US11401786

申请日：2006-04-11

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L21/336

CPC分类号： H01L27/1211 ,  H01L21/845 ,  H01L27/11 ,  H01L29/66795 ,  H01L29/785 ,  Y10S257/903

摘要： A compact semiconductor structure having back gate(s) for controlling threshold voltages and associated method of formation is disclosed. Fabrication of the semiconductor structure starts with a semiconductor region formed directly on an underlying electrically isolating layer. Then, a mandrel and a spacer are formed on the semiconductor region. Next, a back gate region is formed separated from the semiconductor region by a back gate isolating layer and covered by an inter-gate isolating layer. Next, a portion of the semiconductor region beneath the mandrel is removed so as to form an active region adjacent to the removed portion of the semiconductor region. Finally, a main gate region is formed in place of the removed portion of the semiconductor region and on the inter-gate isolating layer. The main gate region is separated from the active region by a main gate isolating layer and separated from the back gate region by the inter-gate isolating layer.

公开(公告)号：US20060163673A1

公开(公告)日：2006-07-27

申请号：US11340354

申请日：2006-01-26

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/66553 ,  H01L29/66795

摘要： A field effect transistor (FET) comprising an isolation layer, a source region positioned over the isolation layer, a drain region positioned over the isolation layer, a bifurcated silicide gate region positioned over the channel region, and a gate oxide layer adjacent to the gate region, wherein the gate oxide layer comprises an alkali metal ion implanted at a dosage calculated based on threshold voltage test data provided by a post silicide electrical test conducted on said FET, wherein the alkali metal ion comprises any of cesium and rubidium.

摘要翻译： 包括隔离层的场效应晶体管（FET），位于隔离层上方的源极区域，位于隔离层上方的漏极区域，位于沟道区域上方的分叉硅化物栅极区域以及邻近栅极的栅氧化层 区，其中所述栅极氧化物层包含以基于通过在所述FET上进行的后硅化物电测试提供的阈值电压测试数据计算的剂量注入的碱金属离子，其中所述碱金属离子包含任何铯和铷。