公开(公告)号：US20070263472A1

公开(公告)日：2007-11-15

申请号：US11382722

申请日：2006-05-11

申请人： Brent Anderson ,  Edward Nowak ,  Noah Zamdmer

发明人： Brent Anderson ,  Edward Nowak ,  Noah Zamdmer

IPC分类号： G11C8/00 ,  H01L21/8234 ,  H01L29/788 ,  H01L21/336

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： Structures and methods are disclosed for evaluating the effect of a process environment variation. A structure and related method are disclosed including a plurality of electrical structures arranged in a non-collinear fashion for determining a magnitude and direction of a process environment variation in the vicinity of the plurality of electrical structures. The plurality of structures may include a first polarity FET coupled to a second polarity FET, each of the first polarity FET and the second polarity FET are coupled to a first pad and a second pad such that the structure allows independent measurement of the first polarity FET and the second polarity FET using only the first and second pads. Alternatively, the electrical structures may include resistors, diodes or ring oscillators. Appropriate measurements of each electrical structure allow a gradient field including a magnitude and direction of the effect of a process environment variation to be determined.

摘要翻译： 公开了用于评估过程环境变化的影响的结构和方法。 公开了一种结构和相关方法，其包括以非共线方式布置的多个电结构，用于确定多个电结构附近的工艺环境变化的大小和方向。 多个结构可以包括耦合到第二极性FET的第一极性FET，第一极性FET和第二极性FET中的每一个耦合到第一焊盘和第二焊盘，使得该结构允许独立测量第一极性FET 和仅使用第一和第二焊盘的第二极性FET。 或者，电气结构可以包括电阻器，二极管或环形振荡器。 每个电气结构的适当测量允许确定包括过程环境变化的影响的幅度和方向的梯度场。

公开(公告)号：US20070235818A1

公开(公告)日：2007-10-11

申请号：US11277677

申请日：2006-03-28

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L21/823807 ,  H01L21/823828 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78687

摘要： Embodiments herein present a device, method, etc. for a dual-plane complementary metal oxide semiconductor. The device comprises a fin-type transistor on a bulk silicon substrate. The fin-type transistor comprises outer fin regions and a center semiconductor fin region, wherein the center fin region has a {110} crystalline oriented channel surface. The outer fin regions comprise a strain inducing impurity that stresses the center semiconductor fin region. The strain inducing impurity contacts the bulk silicon substrate, wherein the strain inducing impurity comprises germanium and/or carbon. Further, the fin-type transistor comprises a thick oxide member on a top face thereof. The fin-type transistor also comprises a first transistor on a first crystalline oriented surface, wherein the device further comprises a second transistor on a second crystalline oriented surface that differs from the first crystalline oriented surface.

摘要翻译： 本文的实施方案提供了用于双平面互补金属氧化物半导体的器件，方法等。 该器件包括在体硅衬底上的鳍式晶体管。 鳍型晶体管包括外鳍区域和中心半导体鳍片区域，其中中心鳍片区域具有{110}晶体取向沟道表面。 外鳍区域包括应力诱导杂质的应变中心半导体鳍片区域的应变。 诱发杂质的应变接触体硅衬底，其中应变诱导杂质包括锗和/或碳。 此外，鳍型晶体管在其顶面包括厚氧化物构件。 翅片型晶体管还包括在第一晶体取向表面上的第一晶体管，其中该器件还包括与第一结晶定向表面不同的第二晶体取向表面上的第二晶体管。

公开(公告)号：US20070212857A1

公开(公告)日：2007-09-13

申请号：US11749417

申请日：2007-05-16

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L21/20

CPC分类号： H01L27/1207 ,  H01L21/76275 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/1203

摘要： An integrated circuit having devices fabricated in both SOI regions and bulk regions, wherein the regions are connected by a trench filled with epitaxially deposited material. The filled trench provides a continuous semiconductor surface joining the SOI and bulk regions. The SOI and bulk regions may have the same or different crystal orientations. The present integrated circuit is made by forming a substrate with SOI and bulk regions separated by an embedded sidewall spacer (made of dielectric). The sidewall spacer is etched, forming a trench that is subsequently filled with epitaxial material. After planarizing, the substrate has SOI and bulk regions with a continuous semiconductor surface. A butted P-N junction and silicide layer can provide electrical connection between the SOI and bulk regions.

摘要翻译： 具有在SOI区域和体区域中制造的器件的集成电路，其中所述区域通过填充有外延沉积材料的沟槽连接。 填充的沟槽提供连接SOI和块区域的连续的半导体表面。 SOI和体区可以具有相同或不同的晶体取向。 本集成电路通过形成具有由嵌入式侧壁间隔物（由电介质制成）隔开的SOI和主体区域的衬底制成。 蚀刻侧壁间隔物，形成随后用外延材料填充的沟槽。 在平坦化之后，衬底具有SOI和具有连续半导体表面的体区。 对接的P-N结和硅化物层可以在SOI和体区之间提供电连接。

公开(公告)号：US20070023756A1

公开(公告)日：2007-02-01

申请号：US11161213

申请日：2005-07-27

申请人： Brent Anderson ,  Matthew Breitwisch ,  Edward Nowak ,  BethAnn Rainey

发明人： Brent Anderson ,  Matthew Breitwisch ,  Edward Nowak ,  BethAnn Rainey

IPC分类号： H01L29/12 ,  H01L21/84

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78615 ,  H01L29/78687

摘要： A field effect transistor (FET) and method of forming the FET comprises a substrate; a silicon germanium (SiGe) layer over the substrate; a semiconductor layer over and adjacent to the SiGe layer; an insulating layer adjacent to the substrate, the SiGe layer, and the semiconductor layer; a pair of first gate structures adjacent to the insulating layer; and a second gate structure over the insulating layer. Preferably, the insulating layer is adjacent to a side surface of the SiGe layer and an upper surface of the semiconductor layer, a lower surface of the semiconductor layer, and a side surface of the semiconductor layer. Preferably, the SiGe layer comprises carbon. Preferably, the pair of first gate structures are substantially transverse to the second gate structure. Additionally, the pair of first gate structures are preferably encapsulated by the insulating layer.

摘要翻译： 场效应晶体管（FET）和形成FET的方法包括：衬底; 衬底上的硅锗（SiGe）层; 在SiGe层上并邻近SiGe层的半导体层; 与衬底相邻的绝缘层，SiGe层和半导体层; 邻近绝缘层的一对第一栅极结构; 以及绝缘层上的第二栅极结构。 优选地，绝缘层与SiGe层的侧表面，半导体层的上表面，半导体层的下表面和半导体层的侧表面相邻。 优选地，SiGe层包含碳。 优选地，该对第一栅极结构基本上横向于第二栅极结构。 此外，该对第一栅极结构优选地被绝缘层封装。

公开(公告)号：US20060234456A1

公开(公告)日：2006-10-19

申请号：US11426623

申请日：2006-06-27

申请人： Brent Anderson ,  William Clark ,  Edward Nowak

发明人： Brent Anderson ,  William Clark ,  Edward Nowak

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66795 ,  H01L29/7887 ,  Y10S438/954

摘要： A four-bit FinFET memory cell, a method of fabricating a four-bit FinFET memory cell and an NVRAM formed of four-bit FINFET memory cells. The four-bit memory cell including two charge storage regions in opposite ends of a dielectric layer on a first sidewall of a fin of a FinFET and two additional charge storage regions in opposite ends of a dielectric layer on a second sidewall of the fin of the FinFET, the first and second sidewalls being opposite one another.

摘要翻译： 四位FinFET存储单元，制造四位FinFET存储单元的方法和由四位FINFET存储单元形成的NVRAM。 该四位存储单元包括在FinFET的鳍的第一侧壁上的电介质层的相对端中的两个电荷存储区，以及位于鳍的翅片的第二侧壁上的电介质层的相对端中的两个附加电荷存储区 FinFET，第一和第二侧壁彼此相对。

公开(公告)号：US20060097329A1

公开(公告)日：2006-05-11

申请号：US10904357

申请日：2004-11-05

申请人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

发明人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L27/1203 ,  H01L29/66795

摘要： A fin-type field effect transistor (FinFET) has a fin having a center channel portion, end portions comprising source and drain regions, and channel extensions extending from sidewalls of the channel portion of the fin. The structure also includes a gate insulator covering the channel portion and the channel extensions, and a gate conductor on the gate insulator. The channel extensions increase capacitance of the channel portion of the fin.

摘要翻译： 翅片型场效应晶体管（FinFET）具有鳍状物，其具有中心沟道部分，端部包括源极和漏极区域以及从鳍片的沟道部分的侧壁延伸的沟道延伸部。 该结构还包括覆盖沟道部分和沟道延伸部的栅极绝缘体以及栅极绝缘体上的栅极导体。 通道扩展增加了鳍片的通道部分的电容。

公开(公告)号：US20060076623A1

公开(公告)日：2006-04-13

申请号：US11270708

申请日：2005-11-09

申请人： Brent Anderson ,  MeiKei Leong ,  Edward Nowak

发明人： Brent Anderson ,  MeiKei Leong ,  Edward Nowak

IPC分类号： H01L27/12 ,  H01L29/788

CPC分类号： H01L21/76251 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785 ,  Y10S438/982

摘要： Disclosed is an integrated circuit structure that has a substrate having at least two types of crystalline orientations. First-type transistors (e.g., NFETs) are formed on first portions of the substrate having a first type of crystalline orientation, and second-type transistors (e.g., PFETs) are formed on second portions of the substrate having a second type of crystalline orientation. Some of the first portions of the substrate comprise non-floating substrate portions, and the remaining ones of the first portions and all of the second portions of the substrate comprise floating substrate portions.

公开(公告)号：US20050275045A1

公开(公告)日：2005-12-15

申请号：US10710007

申请日：2004-06-11

申请人： Brent Anderson ,  Andres Bryant ,  William Clark ,  Edward Nowak

发明人： Brent Anderson ,  Andres Bryant ,  William Clark ,  Edward Nowak

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/7833 ,  H01L29/1045 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/66583 ,  H01L29/7835 ,  H01L29/785

摘要： A field effect transistor (FET) has underlap regions adjacent to the channel doping region. The underlap regions have very low dopant concentrations of less than 1×1017/cc or 5×1016/cc and so tend to have a high resistance. The underlap regions reduce overlap capacitance and thereby increase switching speed. High resistance of the underlap regions is not problematic at subthreshold voltages because the channel doping region also has a high resistance at subthreshold voltages. Consequently, the present FET has low capacitance and high speed and is particularly well suited for operation in the subthreshold regime.

摘要翻译： 场效应晶体管（FET）具有与沟道掺杂区域相邻的底部区域。 底层区域具有小于1×10 17 / cc或5×10 16 / cc的非常低的掺杂剂浓度，因此倾向于具有高电阻。 下层区域减少重叠电容，从而提高开关速度。 欠电压区域的高电阻在亚阈值电压下是没有问题的，因为沟道掺杂区域在亚阈值电压下也具有高电阻。 因此，本FET具有低电容和高速度，并且特别适合于在亚阈值状态下操作。

公开(公告)号：US20080090361A1

公开(公告)日：2008-04-17

申请号：US11866435

申请日：2007-10-03

申请人： Brent Anderson ,  Andres Bryant ,  Jeffrey Johnson ,  Edward Nowak

发明人： Brent Anderson ,  Andres Bryant ,  Jeffrey Johnson ,  Edward Nowak

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795

摘要： Disclosed are embodiments of a trigate field effect transistor that comprises a fin-shaped semiconductor body with a channel region and source/drain regions on either side of the channel region. Thick gate dielectric layers separate the top surface and opposing sidewalls of the channel region from the gate conductor in order to suppress conductivity in the channel planes. A thin gate dielectric layer separates the upper corners of the channel region from the gate conductor in order to optimize conductivity in the channel corners. To further emphasize the current flow in the channel corners, the source/drain regions can be formed in the upper corners of the semiconductor body alone. Alternatively, source/drain extension regions can be formed only in the upper corners of the semiconductor body adjacent to the gate conductor and deep source/drain diffusion regions can be formed in the ends of the semiconductor body.

摘要翻译： 公开了一种触发场效应晶体管的实施例，其包括具有沟道区的鳍状半导体本体和沟道区两侧的源极/漏极区。 厚栅电介质层将沟道区的顶表面和相对的侧壁与栅极导体分开，以便抑制沟道平面中的导电性。 薄栅极电介质层将沟道区的上角与栅极导体分开，以便优化沟道角中的导电性。 为了进一步强调通道角中的电流流动，源极/漏极区域可以单独形成在半导体主体的上角部。 或者，源极/漏极延伸区域仅可以形成在与栅极导体相邻的半导体本体的上角处，并且可以在半导体本体的端部形成深的源极/漏极扩散区域。

公开(公告)号：US20080036000A1

公开(公告)日：2008-02-14

申请号：US11876830

申请日：2007-10-23

申请人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

发明人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/66772 ,  H01L29/665 ,  H01L29/78645 ,  H01L29/78648

摘要： A semiconductor structure and the associated method for fabricating the same. The semiconductor structure includes (a) a semiconductor substrate, (b) a back gate region on the semiconductor substrate, (c) a back gate dielectric region on the back gate region, (d) a semiconductor region on the back gate dielectric region comprising a channel region disposed between first and second source/drain (S/D) regions, (e) a main gate dielectric region on the semiconductor region, (f) a main gate region on the main gate dielectric region, (g) a first contact pad adjacent to the first S/D region and electrically insulated from the back gate region, and (h) a first buried dielectric region that physically and electrically isolates the first contact pad and the back gate region, and wherein the first buried dielectric region has a first thickness in the first direction at least 1.5 times a second thickness of the back gate region.

摘要翻译： 半导体结构及其制造方法。 半导体结构包括（a）半导体衬底，（b）半导体衬底上的背栅区，（c）背栅区上的背栅电介质区，（d）背栅电介质区上的半导体区，包括 设置在第一和第二源极/漏极（S / D）区域之间的沟道区域，（e）半导体区域上的主栅极电介质区域，（f）主栅极电介质区域上的主栅极区域，（g） 接触垫，其与所述第一S / D区相邻并且与所述背栅区电绝缘，以及（h）物理地和电隔离所述第一接触焊盘和所述背栅区的第一掩埋介电区，并且其中所述第一掩埋介电区 在第一方向上具有至少1.5倍于后栅极区域的第二厚度的第一厚度。