公开(公告)号：US20080090361A1

公开(公告)日：2008-04-17

申请号：US11866435

申请日：2007-10-03

申请人： Brent Anderson ,  Andres Bryant ,  Jeffrey Johnson ,  Edward Nowak

发明人： Brent Anderson ,  Andres Bryant ,  Jeffrey Johnson ,  Edward Nowak

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795

摘要： Disclosed are embodiments of a trigate field effect transistor that comprises a fin-shaped semiconductor body with a channel region and source/drain regions on either side of the channel region. Thick gate dielectric layers separate the top surface and opposing sidewalls of the channel region from the gate conductor in order to suppress conductivity in the channel planes. A thin gate dielectric layer separates the upper corners of the channel region from the gate conductor in order to optimize conductivity in the channel corners. To further emphasize the current flow in the channel corners, the source/drain regions can be formed in the upper corners of the semiconductor body alone. Alternatively, source/drain extension regions can be formed only in the upper corners of the semiconductor body adjacent to the gate conductor and deep source/drain diffusion regions can be formed in the ends of the semiconductor body.

摘要翻译： 公开了一种触发场效应晶体管的实施例，其包括具有沟道区的鳍状半导体本体和沟道区两侧的源极/漏极区。 厚栅电介质层将沟道区的顶表面和相对的侧壁与栅极导体分开，以便抑制沟道平面中的导电性。 薄栅极电介质层将沟道区的上角与栅极导体分开，以便优化沟道角中的导电性。 为了进一步强调通道角中的电流流动，源极/漏极区域可以单独形成在半导体主体的上角部。 或者，源极/漏极延伸区域仅可以形成在与栅极导体相邻的半导体本体的上角处，并且可以在半导体本体的端部形成深的源极/漏极扩散区域。

公开(公告)号：US20080036000A1

公开(公告)日：2008-02-14

申请号：US11876830

申请日：2007-10-23

申请人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

发明人： Brent Anderson ,  Andres Bryant ,  Edward Nowak

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/66772 ,  H01L29/665 ,  H01L29/78645 ,  H01L29/78648

摘要： A semiconductor structure and the associated method for fabricating the same. The semiconductor structure includes (a) a semiconductor substrate, (b) a back gate region on the semiconductor substrate, (c) a back gate dielectric region on the back gate region, (d) a semiconductor region on the back gate dielectric region comprising a channel region disposed between first and second source/drain (S/D) regions, (e) a main gate dielectric region on the semiconductor region, (f) a main gate region on the main gate dielectric region, (g) a first contact pad adjacent to the first S/D region and electrically insulated from the back gate region, and (h) a first buried dielectric region that physically and electrically isolates the first contact pad and the back gate region, and wherein the first buried dielectric region has a first thickness in the first direction at least 1.5 times a second thickness of the back gate region.

摘要翻译： 半导体结构及其制造方法。 半导体结构包括（a）半导体衬底，（b）半导体衬底上的背栅区，（c）背栅区上的背栅电介质区，（d）背栅电介质区上的半导体区，包括 设置在第一和第二源极/漏极（S / D）区域之间的沟道区域，（e）半导体区域上的主栅极电介质区域，（f）主栅极电介质区域上的主栅极区域，（g） 接触垫，其与所述第一S / D区相邻并且与所述背栅区电绝缘，以及（h）物理地和电隔离所述第一接触焊盘和所述背栅区的第一掩埋介电区，并且其中所述第一掩埋介电区 在第一方向上具有至少1.5倍于后栅极区域的第二厚度的第一厚度。

公开(公告)号：US20070187769A1

公开(公告)日：2007-08-16

申请号：US11276135

申请日：2006-02-15

申请人： Brent Anderson ,  Andres Bryant ,  William Clark ,  Edward Nowak

发明人： Brent Anderson ,  Andres Bryant ,  William Clark ,  Edward Nowak

IPC分类号： H01L21/337 ,  H01L29/94

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/11

摘要： Disclosed are embodiments of a structure that comprises a first device, having multiple FETs, and a second device, having at least one FET. Sections of a first portion of a semiconductor layer below the first device are doped and contacted to form back gates. A second portion of the semiconductor layer below the second device remains un-doped and un-contacted and, thus, functions as an insulator. Despite the performance degradation of the first device due to back gate capacitance, the back gates result in a net gain for devices such as, SRAM cells, which require precise Vt control. Contrarily, despite marginal Vt control in the second device due to the absence of back gates, the lack of capacitance loading and the added insulation result in a net gain for high performance devices such as, logic circuits.

摘要翻译： 公开了包括具有多个FET的第一器件和具有至少一个FET的第二器件的结构的实施例。 第一器件下方的半导体层的第一部分的部分被掺杂并接触以形成后栅极。 第二器件下方的半导体层的第二部分保持未掺杂和未接触，并因此用作绝缘体。 尽管由于背栅电容而导致第一器件的性能下降，但是后栅导致需要精确Vt控制的诸如SRAM单元的器件的净增益。 相反，尽管由于不存在后门而导致第二器件中的边缘Vt控制，但由于缺少电容负载和增加的绝缘，导致高性能器件（如逻辑电路）的净增益。

公开(公告)号：US20070158762A1

公开(公告)日：2007-07-12

申请号：US11275513

申请日：2006-01-11

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L21/823456 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

摘要： Disclosed are planar and non-planar field effect transistor (FET) structures and methods of forming the structures. The structures comprise segmented active devices (e.g., multiple semiconductor fins for a non-planar transistor or multiple semiconductor layer sections for a planar transistor) connected at opposite ends to source/drain bridges. A gate electrode is patterned on the segmented active devices between the source/drain bridges such that it has a reduced length between the segments (i.e., between the semiconductor fins or sections). Source/drain contacts land on the source/drain bridges such that they are opposite only those portions of the gate electrode with the reduced gate length. These FET structures can be configured to simultaneously maximize the density of the transistor, minimize leakage power and maintain the parasitic capacitance between the source/drain contacts and the gate conductor below a preset level, depending upon the performance and density requirements.

摘要翻译： 公开了平面和非平面场效应晶体管（FET）结构和形成结构的方法。 这些结构包括在源极/漏极桥两端连接的分段有源器件（例如，用于非平面晶体管的多个半导体鳍片或用于平面晶体管的多个半导体层部分）。 在源极/漏极桥之间的分段有源器件上图案化栅电极，使得栅极电极在段之间（即，半导体鳍片或部分之间）具有减小的长度。 源极/漏极接触器接地在源/漏极桥上，使得它们仅与具有减小的栅极长度的栅电极的那些部分相对。 这些FET结构可以被配置为同时使晶体管的密度最大化，从而使漏极功率最小化，并且将源极/漏极触点和栅极导体之间​​的寄生电容保持在预定值以下，这取决于性能和密度要求。

公开(公告)号：US20070158752A1

公开(公告)日：2007-07-12

申请号：US11275492

申请日：2006-01-10

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L29/94

CPC分类号： H01L29/7843 ,  H01L27/11 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a semiconductor structure and associated method of performing the structure with good performance and stability trade-offs for digital circuits and SRAM cells and/or analog FETs on the same chip. Specifically, a dual-strain layer is formed over digital circuits and the other devices on a chip. The dual-strain layer comprises tensile sections above digital logic n-type transistors, compressive sections above digital logic p-type transistors and additional tensile sections above SRAM cells and/or analog FETs. An amorphization ion-implant is performed to relax the strain over SRAM cell p-FETs and, thereby, eliminate variability and avoid p-FET performance degradation in the SRAM cells. Additionally, this ion-implant can relax the strain above both analog p-FETs and n-FETs and, thereby, eliminate variability and the coupling of the logic device process to the analog FETs and provide more predictable and well-controlled analog FETs.

摘要翻译： 公开了一种在相同芯片上执行数字电路和SRAM单元和/或模拟FET的良好性能和稳定性权衡的结构的半导体结构和相关方法。 具体地说，在数字电路和芯片上的其它器件上形成双应变层。 双应变层包括位于数字逻辑n型晶体管之上的拉伸部分，位于数字逻辑p型晶体管之上的压缩部分以及SRAM单元和/或模拟FET之上的附加拉伸部分。 执行非晶化离子注入以松弛SRAM单元p-FET上的应变，从而消除SRAM单元中的可变性并避免p-FET性能下降。 此外，该离子注入可以松弛模拟p-FET和n-FET两者之上的应变，从而消除逻辑器件工艺与模拟FET的可变性和耦合，并提供更可预测和良好控制的模拟FET。

公开(公告)号：US20070063230A1

公开(公告)日：2007-03-22

申请号：US11162660

申请日：2005-09-19

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L29/80

CPC分类号： H01L27/1211 ,  H01L21/823807 ,  H01L21/845 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/7856

摘要： A CMOS device comprising a FinFET comprises at least one fin structure comprising a source region; a drain region; and a channel region comprising silicon separating the source region from the drain region. The FinFET further comprises a gate region over the source region and the drain region and partitioning the fin structure into a first side and a second side, wherein the channel region is in mechanical compression on the first side and in mechanical tension on the second side. The FinFET may comprise any of a nFET and a pFET, wherein the nFET comprises a N-channel inversion region in the second side, and wherein the pFET comprises a P-channel inversion region in the second side. The CMOS device may further comprise a tensile film and a relaxed film on opposite sides of the fin structure, and an oxide cap layer over the fin structure.

摘要翻译： 包括FinFET的CMOS器件包括至少一个鳍结构，其包括源极区; 漏区; 以及包括将源区域与漏极区分离的沟道区域。 FinFET还包括在源极区域和漏极区域上的栅极区域，并且将鳍状结构分隔成第一侧面和第二侧面，其中沟道区域在第一侧上处于机械压缩并且在第二侧上处于机械张力。 FinFET可以包括nFET和pFET中的任一个，其中nFET包括第二侧中的N沟道反转区，并且其中pFET包括第二面中的P沟道反转区。 CMOS器件还可以包括在鳍结构的相对侧上的拉伸膜和松弛膜，以及在翅片结构上方的氧化物盖层。

公开(公告)号：US20060151834A1

公开(公告)日：2006-07-13

申请号：US10905616

申请日：2005-01-13

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L29/772 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/78603

摘要： An integrated circuit structure has a buried oxide (BOX) layer above a substrate, and a first-type fin-type field effect transistor (FinFET) and a second-type FinFET above the BOX layer. The second region of the BOX layer includes a seed opening to the substrate. The top of the first-type FinFET and the second-type FinFET are planar with each other. A first region of the BOX layer below the first FinFET fin is thicker above the substrate when compared to a second region of the BOX layer below the second FinFET fin. Also, the second FinFET fin is taller than the first FinFET fin. The height difference between the first fin and the second fin permits the first-type FinFET to have the same drive strength as the second-type FinFET.

摘要翻译： 集成电路结构在衬底上方具有掩埋氧化物（BOX）层，以及在BOX层上方的第一型鳍型场效应晶体管（FinFET）和第二类型FinFET。 BOX层的第二区域包括到基板的种子开口。 第一型FinFET和第二型FinFET的顶部彼此平坦。 当与第二FinFET鳍片下面的BOX层的第二区域相比时，第一FinFET鳍片下面的BOX层的第一区域比衬底上方更厚。 此外，第二个FinFET鳍片比第一个FinFET鳍片高。 第一鳍片和第二鳍片之间的高度差允许第一类型的FinFET具有与第二类型FinFET相同的驱动强度。

公开(公告)号：US20060060856A1

公开(公告)日：2006-03-23

申请号：US10711453

申请日：2004-09-20

申请人： Brent Anderson ,  Louis Lanzerotti ,  Edward Nowak

发明人： Brent Anderson ,  Louis Lanzerotti ,  Edward Nowak

IPC分类号： H01L29/76 ,  H01L21/84

CPC分类号： H01L29/0847 ,  H01L21/8213 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： A field effect transistor and method of fabricating the field effect transistor. The field effect transistor, including: a gate electrode formed on a top surface of a gate dielectric layer, the gate dielectric layer on a top surface of a single-crystal silicon channel region, the single-crystal silicon channel region on a top surface of a Ge including layer, the Ge including layer on a top surface of a single-crystal silicon substrate, the Ge including layer between a first dielectric layer and a second dielectric layer on the top surface of the single-crystal silicon substrate.

摘要翻译： 场效应晶体管和制造场效应晶体管的方法。 该场效应晶体管包括：形成在栅极电介质层的顶表面上的栅电极，单晶硅沟道区的顶表面上的栅介质层，顶表面上的单晶硅沟道区 包含Ge的层，在单晶硅衬底的顶表面上的Ge包括层，在单晶硅衬底的顶表面上的第一介电层和第二电介质层之间的Ge包括层。

公开(公告)号：US20060022253A1

公开(公告)日：2006-02-02

申请号：US10710680

申请日：2004-07-28

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L29/788

CPC分类号： H01L29/42328 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7881

摘要： Disclosed is a multiple-gate transistor that includes a channel region and source and drain regions at ends of the channel region. A gate oxide is positioned between a logic gate and the channel region and a first insulator is formed between a floating gate and the channel region. The first insulator is thicker than the gate oxide. The floating gate is electrically insulated from other structures. Also, a second insulator is positioned between a programming gate and the floating gate. Voltage in the logic gate causes the transistor to switch on and off, while stored charge in the floating gate adjusts the threshold voltage of the transistor. The transistor can comprise a fin-type field effect transistor (FinFET), where the channel region comprises the middle portion of a fin structure and the source and drain regions comprise end portions of the fin structure.

摘要翻译： 公开了一种多栅极晶体管，其在沟道区的端部包括沟道区和源极和漏极区。 栅极氧化物位于逻辑栅极和沟道区之间，并且在浮置栅极和沟道区域之间形成第一绝缘体。 第一绝缘体比栅极氧化物厚。 浮动栅极与其他结构电绝缘。 此外，第二绝缘体位于编程门和浮动栅极之间。 逻辑门中的电压导致晶体管导通和截止，而浮置栅极中的存储电荷调节晶体管的阈值电压。 晶体管可以包括鳍式场效应晶体管（FinFET），其中沟道区域包括鳍结构的中间部分，并且源区和漏区包括鳍结构的端部。

公开(公告)号：US20050275040A1

公开(公告)日：2005-12-15

申请号：US10709998

申请日：2004-06-11

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L21/8244 ,  H01L21/84 ,  H01L27/11 ,  H01L27/12 ,  H01L29/786 ,  H01L31/113

CPC分类号： H01L27/1211 ,  H01L21/845 ,  H01L27/11 ,  H01L29/66795 ,  H01L29/785 ,  Y10S257/903

摘要： A compact semiconductor structure having back gate(s) for controlling threshold voltages and associated method of formation is disclosed. Fabrication of the semiconductor structure starts with a semiconductor region formed directly on an underlying electrically isolating layer. Then, a mandrel and a spacer are formed on the semiconductor region. Next, a back gate region is formed separated from the semiconductor region by a back gate isolating layer and covered by an inter-gate isolating layer. Next, a portion of the semiconductor region beneath the mandrel is removed so as to form an active region adjacent to the removed portion of the semiconductor region. Finally, a main gate region is formed in place of the removed portion of the semiconductor region and on the inter-gate isolating layer. The main gate region is separated from the active region by a main gate isolating layer and separated from the back gate region by the inter-gate isolating layer.

摘要翻译： 公开了一种具有用于控制阈值电压的背栅的紧凑型半导体结构和相关的形成方法。 半导体结构的制造从直接形成在下面的电绝缘层上的半导体区域开始。 然后，在半导体区域上形成心轴和间隔物。 接下来，通过背栅绝缘层与栅极间隔离层被覆盖的半导体区域形成背栅极区域。 接下来，去除心轴下方的半导体区域的一部分，以形成与半导体区域的去除部分相邻的有源区。 最后，形成主栅极区域代替半导体区域的去除部分和栅极间隔离层。 主栅极区域通过主栅极隔离层与有源区域分离，并且通过栅极间隔离层与背栅极区域分离。