公开(公告)号：US20050074095A1

公开(公告)日：2005-04-07

申请号：US10761778

申请日：2004-01-21

申请人： Wei-Chih Chang ,  Wei-Chian Wang

发明人： Wei-Chih Chang ,  Wei-Chian Wang

IPC分类号： G03B42/02 ,  G06F3/045 ,  H05G1/08

CPC分类号： G06F3/045

摘要： A film positioning device for detection a position of a contact point. The film positioning device includes an X film having a first X terminal and a second X terminal, a Y film having a first Y terminal and a second Y terminal, a first Y switch coupled between the first Y terminal and a ground, a second Y switch coupled between a second Y terminal and a power source, a first X switch coupled between the first X terminal and the ground, a second X switch coupled between the second X terminal and the power source, a first X capacitor coupled between the first X terminal and the second X terminal, and a second Y capacitor coupled between the first Y terminal and the second Y terminal.

摘要翻译： 一种用于检测接触点的位置的胶片定位装置。 胶片定位装置包括具有第一X端子和第二X端子的X膜，具有第一Y端子和第二Y端子的Y膜，耦合在第一Y端子和地之间的第一Y开关，第二Y型端子 开关，其耦合在第二Y端子和电源之间，耦合在第一X端子和地之间的第一X开关，耦合在第二X端子和电源之间的第二X开关，耦合在第一X端子和第一X端子之间的第一X电容器 端子和第二X端子，以及耦合在第一Y端子和第二Y端子之间的第二Y电容器。

公开(公告)号：US06680771B2

公开(公告)日：2004-01-20

申请号：US10071062

申请日：2002-02-07

申请人： Jian-Shen Yu ,  Wei-Chih Chang

发明人： Jian-Shen Yu ,  Wei-Chih Chang

IPC分类号： G02F11343

CPC分类号： G02F1/133707 ,  G02F1/134336 ,  G02F1/1393 ,  G02F2001/134345

摘要： A thin film transistor liquid crystal display generates voltage difference between the lower electrodes, then the generating domains are controlled by the voltage difference. The lower electrode is divided into a narrow electrode and a pixel electrode. The pixel electrode is further divided into a plurality of pixel electrodes. The narrow electrode is coupled to a drain or a source of a thin film transistor, and a portion of the pixel electrode is overlapped on the drain/source of the thin film transistor but insulated to the drain/source of the thin film transistor to generate capacitive coupling and make the voltage level of the narrow electrode exceeds that of the pixel electrode. Thus, a horizontal electric fields is formed to generate multiple domains in a signal pixel.

摘要翻译： 薄膜晶体管液晶显示器产生下电极之间的电压差，则产生区域受电压差的控制。 下电极被分成窄电极和像素电极。 像素电极被进一步分成多个像素电极。 窄电极耦合到薄膜晶体管的漏极或源极，并且像素电极的一部分重叠在薄膜晶体管的漏极/源极上，但与薄膜晶体管的漏极/源极绝缘，以产生 电容耦合，使得窄电极的电压电平超过像素电极的电压。 因此，形成水平电场以在信号像素中产生多个畴。

公开(公告)号：US6072911A

公开(公告)日：2000-06-06

申请号：US59174

申请日：1998-04-13

申请人： Li-Ming Chen ,  Wei-Chih Chang

发明人： Li-Ming Chen ,  Wei-Chih Chang

IPC分类号： G06T5/20 ,  G06K9/56 ,  G06K9/40

CPC分类号： G06T5/20

摘要： A linear image filter and the corresponding filtering method is disclosed. In conventional linear image filters, only one pixel can be processed during a single cycle because it is applied to an odd-order filter matrix. Consequently, the present linear image filter and the corresponding method expand the original odd-order filter matrix into an even-order matrix by adding a row and a column of zeros at the topmost/bottommost and the rightmost/leftmost of the original filter matrix. This not only increases the filtering speed of the linear image filter because four pixels can be simultaneously reconstructed, but also fully utilizes current 32-bit processors because a pixel is currently represented only as an 8-bit value.

摘要翻译： 公开了一种线性图像滤波器和相应的滤波方法。 在传统的线性图像滤波器中，由于将其应用于奇数阶滤波器矩阵，因此在单个周期中只能处理一个像素。 因此，本线性图像滤波器和相应的方法通过在原始滤波器矩阵的最上/最底和最右/最左边添加一行和一列零将原始奇数阶滤波器矩阵扩展为偶数矩阵。 这不仅增加了线性图像滤波器的滤波速度，因为可以同时重构四个像素，而且还充分利用当前的32位处理器，因为像素当前仅被表示为8位值。

公开(公告)号：US08466817B2

公开(公告)日：2013-06-18

申请号：US13282150

申请日：2011-10-26

申请人： Wei-Chih Chang ,  Yu-Peng Lai ,  Ching-Chung Hung

发明人： Wei-Chih Chang ,  Yu-Peng Lai ,  Ching-Chung Hung

IPC分类号： H03M1/10

CPC分类号： H03M1/186

摘要： An electronic device and a method for driving an internal function block of a processor of the electric device to operate in a linear region. The electronic device comprises a processor having two multiple purpose pins (MPP1 and MPP2), an external device connection port, and two resistance elements. The external device connection port is further connected to the MPP1 and at a tested voltage. The first resistance element is connected between a high level voltage and the external device connection port. The second resistance element is connected between the external device connection port and the MPP2. The processor is configured to output the high or low level voltage at MPP2 when the tested voltage is in a non-linear operating region, to guarantee the tested voltage to a linear operating region of the function block which is coupled to the MPP1 by a multiplexing design.

摘要翻译： 一种用于驱动电气设备的处理器的内部功能块以在线性区域中操作的电子设备和方法。 电子设备包括具有两个多用途引脚（MPP1和MPP2），外部设备连接端口和两个电阻元件的处理器。 外部设备连接端口进一步连接到MPP1并处于测试电压。 第一电阻元件连接在高电平电压和外部设备连接端口之间。 第二个电阻元件连接在外部设备连接端口和MPP2之间。 处理器被配置为当测试电压处于非线性工作区域时，在MPP2处输出高电平或低电平电压，以通过多路复用来保证被测电压到功能块的线性工作区，该功能块与MPP1耦合 设计。

公开(公告)号：US08212590B2

公开(公告)日：2012-07-03

申请号：US13067598

申请日：2011-06-13

申请人： Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang

发明人： Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang

IPC分类号： H03B1/00

CPC分类号： H03K19/0013 ,  H03K3/356113 ,  H03K19/018521

摘要： A mixed-voltage I/O buffer includes an input buffer circuit. The input buffer circuit includes a first inverter, a first voltage level limiting circuit, a first voltage level pull-up circuit, an input stage circuit, and a logic calibration circuit. The first inverter inverts an input signal to generate a first control signal. The first voltage level limiting circuit limits voltage level of an external signal to generate the input signal transmitted to the first inverter to prevent electrical overstress of the first inverter. The first voltage level pull-up circuit is controlled by the first control signal to pull up voltage level of the input signal inputted into the first inverter. The input stage circuit receives the first control signal to generate corresponding digital signals inputted into a core circuit. The logic calibration circuit calibrates voltage level of the first control signal when the first inverter mis-operates due to the input signal having a low voltage level.

摘要翻译： 混合电压I / O缓冲器包括输入缓冲电路。 输入缓冲电路包括第一反相器，第一电压电平限制电路，第一电压电平上拉电路，输入级电路和逻辑校准电路。 第一反相器反相输入信号以产生第一控制信号。 第一电压电平限制电路限制外部信号的电压电平，以产生传输到第一逆变器的输入信号，以防止第一逆变器的电过载。 第一电压上拉电路由第一控制信号控制，以提高输入到第一反相器的输入信号的电压电平。 输入级电路接收第一控制信号以产生输入到核心电路的相应的数字信号。 当由于输入信号具有低电压电平而使第一反相器误操作时，逻辑校准电路校准第一控制信号的电压电平。

公开(公告)号：US20120042550A1

公开(公告)日：2012-02-23

申请号：US13206616

申请日：2011-08-10

申请人： Wei-Yu Chang ,  Wei-Chih Chang

发明人： Wei-Yu Chang ,  Wei-Chih Chang

IPC分类号： G09F3/18 ,  G09F3/00

CPC分类号： G09F3/207 ,  A44B15/005 ,  G09F3/14

摘要： A key tag includes: a body having a recess and a through hole near its one end, a tag sheet accommodated in the recess, and a cover sheet adaptively engaged with the body so as to confine the tag sheet within the recess.

摘要翻译： 钥匙标签包括：具有凹部和靠近其一端的通孔的本体，容纳在凹部中的标签片，以及与本体自适应地接合以将标签片限制在凹部内的盖片。

公开(公告)号：US07884029B2

公开(公告)日：2011-02-08

申请号：US12480697

申请日：2009-06-09

申请人： Shih-Cheng Lin ,  Wei-Chih Chang ,  Yi-Chin Chou ,  Chorng-Jye Huang ,  Pin-Sheng Wang

发明人： Shih-Cheng Lin ,  Wei-Chih Chang ,  Yi-Chin Chou ,  Chorng-Jye Huang ,  Pin-Sheng Wang

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L31/022425 ,  B32B17/10018 ,  B32B17/10788 ,  B32B2327/12 ,  H01L31/048 ,  H01L31/068 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： A solar cell having an improved structure of rear surface includes a p-type doped region, a dense metal layer, a loose metal layer, at least one bus bar opening, and solderable material on or within the bus bar opening. The solderable material contacts with the dense aluminum layer. The improved structure in rear surface increases the light converting efficiency, and provides a good adhesion between copper ribbon and solar cell layer thereby providing cost advantages and reducing the complexity in manufacturing. A solar module and solar system composed of such solar cell are also disclosed.

摘要翻译： 具有改进的后表面结构的太阳能电池包括p型掺杂区域，致密金属层，松散金属层，至少一个汇流条开口以及汇流条开口上或其内部的可焊接材料。 可焊接材料与致密的铝层接触。 后表面的改进结构提高了光转换效率，并且提供了铜带和太阳能电池层之间的良好粘附性，从而提供成本优势并降低了制造的复杂性。 还公开了由太阳能电池组成的太阳能模块和太阳能系统。

公开(公告)号：US20100277216A1

公开(公告)日：2010-11-04

申请号：US12835202

申请日：2010-07-13

申请人： Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang ,  Tie-Yan Chang

发明人： Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang ,  Tie-Yan Chang

IPC分类号： H03L5/00

CPC分类号： H03K19/018521 ,  H03K19/018528

摘要： An output buffer circuit is provided. The output buffer circuit receives a control signal (OE) and a data signal (Dout) from a first core circuit (10) and operates in a transmitting mode according to the control signal. The output buffer circuit converts the data signal into an output signal at a first voltage level or a ground voltage level according to the data signal logic level and a supply voltage (VDDIO). The supply voltage is adjusted to pull up or pull down the first voltage level of the output signal.

摘要翻译： 提供输出缓冲电路。 输出缓冲电路从第一核心电路（10）接收控制信号（OE）和数据信号（Dout），并根据控制信号在发送模式下工作。 输出缓冲电路根据数据信号逻辑电平和电源电压（VDDIO）将数据信号转换成第一电压电平或接地电压电平的输出信号。 电源电压被调整为上拉或下拉输出信号的第一电压电平。

公开(公告)号：US07786760B2

公开(公告)日：2010-08-31

申请号：US12193299

申请日：2008-08-18

申请人： Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang ,  Tie-Yan Chang

发明人： Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang ,  Tie-Yan Chang

IPC分类号： H03K19/0175

CPC分类号： H03K19/018521 ,  H03K19/018528

摘要： An output buffer circuit is provided. The output buffer circuit receives a control signal (OE) and a data signal (Dout) from a first core circuit (10) and operates in a transmitting mode according to the control signal. The output buffer circuit converts the data signal into an output signal at a first voltage level or a ground voltage level according to the data signal logic level and a supply voltage (VDDIO). The supply voltage is adjusted to pull up or pull down the first voltage level of the output signal.

摘要翻译： 提供输出缓冲电路。 输出缓冲电路从第一核心电路（10）接收控制信号（OE）和数据信号（Dout），并根据控制信号在发送模式下工作。 输出缓冲电路根据数据信号逻辑电平和电源电压（VDDIO）将数据信号转换成第一电压电平或接地电压电平的输出信号。 电源电压被调整为上拉或下拉输出信号的第一电压电平。

公开(公告)号：US20090301555A1

公开(公告)日：2009-12-10

申请号：US12480699

申请日：2009-06-09

申请人： Shih-Cheng Lin ,  Wei-Chih Chang ,  Yi-Chin Chou ,  Chorng-Jye Huang ,  Pin-Sheng Wang

发明人： Shih-Cheng Lin ,  Wei-Chih Chang ,  Yi-Chin Chou ,  Chorng-Jye Huang ,  Pin-Sheng Wang

IPC分类号： H01L31/00

CPC分类号： H01L31/022425 ,  B32B17/10018 ,  B32B17/10788 ,  B32B2327/12 ,  H01L31/048 ,  H01L31/068 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： A solar cell having an improved structure of rear surface includes a p-type doped region, a dense metal layer, a loose metal layer, at least one bus bar opening, and solderable material on or within the bus bar opening. The solderable material contacts with the dense aluminum layer. The improved structure in rear surface increases the light converting efficiency, and provides a good adhesion between copper ribbon and solar cell layer thereby providing cost advantages and reducing the complexity in manufacturing. A solar module and solar system composed of such solar cell are also disclosed.

摘要翻译： 具有改进的后表面结构的太阳能电池包括p型掺杂区域，致密金属层，松散金属层，至少一个汇流条开口以及汇流条开口上或其内部的可焊接材料。 可焊接材料与致密的铝层接触。 后表面的改进结构提高了光转换效率，并且提供了铜带和太阳能电池层之间的良好粘附性，从而提供成本优势并降低了制造的复杂性。 还公开了由太阳能电池组成的太阳能模块和太阳能系统。