公开(公告)号：US08835258B2

公开(公告)日：2014-09-16

申请号：US13844926

申请日：2013-03-16

Applicant: Tsung-Yi Huang ,  Huan-Ping Chu

Inventor： Tsung-Yi Huang ,  Huan-Ping Chu

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/0878 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate has an upper surface. The high voltage device includes: a second conductive type buried layer, which is formed in the substrate; a first conductive type well, which is formed between the upper surface and the buried layer; and a second conductive type well, which is connected to the first conductive type well and located at different horizontal positions. The second conductive type well includes a well lower surface, which has a first part and a second part, wherein the first part is directly above the buried layer and electrically coupled to the buried layer; and the second part is not located above the buried layer and forms a PN junction with the substrate.

Abstract translation: 本发明公开了一种高压器件及其制造方法。 高压器件形成在第一导电型衬底中，其中衬底具有上表面。 高压器件包括：形成在衬底中的第二导电型掩埋层; 第一导电型阱，其形成在上表面和埋层之间; 以及第二导电型阱，其连接到第一导电类型阱并且位于不同的水平位置。 第二导电类型阱包括井下表面，其具有第一部分和第二部分，其中第一部分直接在掩埋层的上方并电耦合到掩埋层; 并且第二部分不位于掩埋层的上方并与衬底形成PN结。

公开(公告)号：US08779690B2

公开(公告)日：2014-07-15

申请号：US13134995

申请日：2011-06-22

Applicant: Fu-Sheng Tsai ,  Pei-Cheng Huang

Inventor： Fu-Sheng Tsai ,  Pei-Cheng Huang

IPC: G05F1/00

CPC classification number: H05B33/0827 ,  H05B33/0851

Abstract: The present invention discloses a direct current (DC) light emitting device control circuit with dimming function, and a method thereof, wherein the dimming function is provided in a feedback loop for feeding back a feedback signal from an output terminal to a power switch control circuit; the feedback signal relates to an output current supplied to the DC light emitting device. The present invention adjusts the feedback signal according to the desired brightness of the DC light emitting device. The present invention controls a power switch according to the adjusted feedback signal, such that the output current supplied to the DC light emitting device is adjusted, and accordingly the brightness of the DC light emitting device is adjusted below the full brightness.

Abstract translation: 本发明公开了一种具有调光功能的直流（DC）发光器件控制电路及其方法，其中调光功能设置在用于将反馈信号从输出端子反馈到电源开关控制电路的反馈环路中 ; 反馈信号与提供给DC发光器件的输出电流有关。 本发明根据DC发光装置的期望亮度来调整反馈信号。 本发明根据调整后的反馈信号控制电源开关，使得提供给DC发光装置的输出电流被调节，因此将DC发光装置的亮度调整到全亮度以下。

公开(公告)号：US20140187003A1

公开(公告)日：2014-07-03

申请号：US14201891

申请日：2014-03-09

Applicant: Chih-Fang Huang ,  Chien-Wei Chiu ,  Ting-Fu Chang ,  Tsung-Yu Yang ,  Tsung-Yi Huang

Inventor： Chih-Fang Huang ,  Chien-Wei Chiu ,  Ting-Fu Chang ,  Tsung-Yu Yang ,  Tsung-Yi Huang

IPC: H01L29/66

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/7787

Abstract: The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT includes a semiconductor layer, a barrier layer on the semiconductor layer, a piezoelectric layer on the barrier layer, a gate on the piezoelectric layer, and a source and a drain at two sides of the gate respectively, wherein each bandgap of the semiconductor layer, the barrier layer, and the piezoelectric layer partially but not entirely overlaps the other two bandgaps. The gate is formed for receiving a gate voltage. A two dimensional electron gas (2DEG) is formed in a portion of a junction between the semiconductor layer and the barrier layer but not below at least a portion of the piezoelectric layer, wherein the 2DEG is electrically connected to the source and the drain.

公开(公告)号：US20140151799A1

公开(公告)日：2014-06-05

申请号：US14173571

申请日：2014-02-05

Applicant: Tsung-Yi Huang ,  Chien-Hao Huang

Inventor： Tsung-Yi Huang ,  Chien-Hao Huang

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66689 ,  H01L29/7816

Abstract: The present invention discloses a double diffused drain metal oxide semiconductor (DDDMOS) device and a manufacturing method thereof. The DDDMOS device is formed in a substrate, and includes a first well, a gate, a diffusion region, a source, and a drain. A low voltage device is also formed in the substrate, which includes a second well and a lightly doped drain (LDD) region, wherein the first well and the diffusion region are formed by process steps which also form the second well and the LDD region in the low voltage device, respectively.

Abstract translation: 本发明公开了一种双扩散漏极金属氧化物半导体（DDDMOS）器件及其制造方法。 DDDMOS器件形成在衬底中，并且包括第一阱，栅极，扩散区域，源极和漏极。 在衬底中还形成低电压器件，该器件包括第二阱和轻掺杂漏极（LDD）区，其中第一阱和扩散区通过也形成第二阱的工艺步骤形成，并且LDD区域 低压装置。

公开(公告)号：US08709900B1

公开(公告)日：2014-04-29

申请号：US14146548

申请日：2014-01-02

Applicant: Ching-Yao Yang ,  Tsung-Yi Huang ,  Huan-Ping Chu ,  Hung-Der Su

Inventor： Ching-Yao Yang ,  Tsung-Yi Huang ,  Huan-Ping Chu ,  Hung-Der Su

IPC: H01L21/336

CPC classification number: H01L29/4238 ,  H01L21/28114 ,  H01L21/823425 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.

公开(公告)号：US20140061724A1

公开(公告)日：2014-03-06

申请号：US13597599

申请日：2012-08-29

Applicant: Chih-Fang Huang ,  Chien-Wei Chiu ,  Ting-Fu Chang ,  Tsung-Yu Yang ,  Tsung-Yi Huang

Inventor： Chih-Fang Huang ,  Chien-Wei Chiu ,  Ting-Fu Chang ,  Tsung-Yu Yang ,  Tsung-Yi Huang

IPC: H01L29/778 ,  H01L21/335

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/7787

Abstract: The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT includes a semiconductor layer, a barrier layer on the semiconductor layer, a piezoelectric layer on the barrier layer, a gate on the piezoelectric layer, and a source and a drain at two sides of the gate respectively, wherein each bandgap of the semiconductor layer, the barrier layer, and the piezoelectric layer partially but not entirely overlaps the other two bandgaps. The gate is formed for receiving a gate voltage. A two dimensional electron gas (2DEG) is formed in a portion of a junction between the semiconductor layer and the barrier layer but not below at least a portion of the piezoelectric layer, wherein the 2DEG is electrically connected to the source and the drain.

Abstract translation: 本发明公开了一种高电子迁移率晶体管（HEMT）及其制造方法。 HEMT包括半导体层，半导体层上的势垒层，阻挡层上的压电层，压电层上的栅极，栅极两侧的源极和漏极，其中半导体的每个带隙 层，阻挡层和压电层部分但不完全与其它两个带隙重叠。 栅极形成为用于接收栅极电压。 二维电子气体（2DEG）形成在半导体层和阻挡层之间的结的一部分中，但不在压电层的至少一部分下方，其中2DEG电连接到源极和漏极。

公开(公告)号：US20140055178A1

公开(公告)日：2014-02-27

申请号：US14070518

申请日：2013-11-02

Applicant: Isaac Chen ,  An-Tung Chen

Inventor： Isaac Chen ,  An-Tung Chen

IPC: H03K5/15

CPC classification number: H03K5/15073 ,  G06F1/04 ,  H02J3/01 ,  H02M2003/1586 ,  Y10T307/50 ,  Y10T307/707

Abstract: The present invention discloses an adaptive phase-shifted synchronization clock generation circuit and a method for generating phase-shifted synchronization clock. The adaptive phase-shifted synchronization clock generation circuit includes: a current source generating a current which flows through a node to generate a node voltage on the node; a reverse-proportional voltage generator coupled to the node for generating a voltage which is reverse-proportional to the node voltage; a ramp generator receiving a synchronization input signal and generating a ramp signal; a comparator comparing the reverse-proportional voltage to the ramp signal; and a pulse generator for generating a clock signal according to an output from the comparator.

Abstract translation: 本发明公开了一种自适应相移同步时钟产生电路和一种产生相移同步时钟的方法。 自适应相移同步时钟生成电路包括：电流源，其产生流过节点的电流，以在节点上产生节点电压; 耦合到所述节点的反向比例电压发生器，用于产生与所述节点电压成反比的电压; 斜坡发生器接收同步输入信号并产生斜坡信号; 比较反向比例电压与斜坡信号的比较器; 以及用于根据比较器的输出产生时钟信号的脉冲发生器。

公开(公告)号：US08653594B2

公开(公告)日：2014-02-18

申请号：US13066622

申请日：2011-04-20

Applicant: Ching-Yao Yang ,  Tsung-Yi Huang ,  Huan-Ping Chu ,  Hung-Der Su

Inventor： Ching-Yao Yang ,  Tsung-Yi Huang ,  Huan-Ping Chu ,  Hung-Der Su

IPC: H01L29/66

CPC classification number: H01L29/4238 ,  H01L21/28114 ,  H01L21/823425 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.

公开(公告)号：US08638126B2

公开(公告)日：2014-01-28

申请号：US13352963

申请日：2012-01-18

Applicant: Chieh-Min Lo ,  Tzu-Huan Chiu ,  Chien-Sheng Chen ,  Chien-Ping Lu

Inventor： Chieh-Min Lo ,  Tzu-Huan Chiu ,  Chien-Sheng Chen ,  Chien-Ping Lu

IPC: H03K5/22

CPC classification number: H03F3/45219 ,  H03K5/2481

Abstract: The present invention discloses a rail-to-rail comparator. The rail-to-rail comparator includes: a positive voltage rail providing a positive supply voltage, a ground voltage rail providing a ground voltage, an input stage, and an output stage. The input stage includes: a positive and a negative input terminals for receiving a first input signal and a second input signal; a first differential amplifier circuit, which includes a pair of depletion NMOS transistors to generate a first pair of differential currents; and a second differential amplifier circuit, which includes a pair of native NMOS transistors to generate a second pair of differential currents. The output stage is coupled to the first differential amplifier circuit and the second differential amplifier circuit, and generates an output signal related to a difference between the first input signal and the second input signal.

Abstract translation: 本发明公开了一种轨对轨比较器。 轨到轨比较器包括：提供正电源电压的正电压轨，提供接地电压的接地电压轨，输入级和输出级。 输入级包括：用于接收第一输入信号和第二输入信号的正和负输入端; 第一差分放大器电路，其包括一对耗尽NMOS晶体管，以产生第一对差分电流; 以及第二差分放大器电路，其包括一对天线NMOS晶体管以产生第二对差分电流。 输出级耦合到第一差分放大器电路和第二差分放大器电路，并且产生与第一输入信号和第二输入信号之间的差有关的输出信号。

公开(公告)号：US20130341719A1

公开(公告)日：2013-12-26

申请号：US13529963

申请日：2012-06-21

Applicant: Tsung-Yi Huang ,  Chien-Hao Huang

Inventor： Tsung-Yi Huang ,  Chien-Hao Huang

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7817 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: The present invention discloses a hybrid high voltage device and a manufacturing method thereof. The hybrid high voltage device is formed in a first conductive type substrate, and includes at least one lateral double diffused metal oxide semiconductor (LDMOS) device region and at least one vent device region, wherein the LDMOS device region and the vent device region are connected in a width direction and arranged in an alternating order. Besides, corresponding high voltage wells, sources, drains, body regions, and gates of the LDMOS device region and the vent device region are connected to each other respectively.

Abstract translation: 本发明公开了一种混合式高压装置及其制造方法。 混合高压器件形成在第一导电型衬底中，并且包括至少一个横向双扩散金属氧化物半导体（LDMOS）器件区域和至少一个通气器件区域，其中LDMOS器件区域和通气器件区域被连接 在宽度方向上以交替的顺序布置。 此外，LDMOS器件区域和通风装置区域的相应的高压井，源极，漏极，体区和栅极分别彼此连接。