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61.发明申请公开(公告)号：US20180349115A1
公开(公告)日：2018-12-06
申请号：US15609583
申请日：2017-05-31
Applicant: Intel Corporation
Inventor： Yongzhi Zhang
CPC classification number: G06F8/433 , G06F8/20 , G06F15/825
Abstract: An apparatus for automatically converting a control flow program into a data flow program comprises a non-transitory machine-readable medium and a translator stored in the machine-readable medium. The translator, when executed by a data processing system, enables the data processing system to (a) automatically generate a control dependency graph for a control flow program, (b) automatically generate a data flow graph based at least in part on the control dependency graph, and (c) automatically generate a data flow program based at least in part on the data flow graph. In one embodiment or scenario, the translator may also automatically insert a switch instruction into the data flow program, in response to a determination that a variable of the control flow program is defined in one control dependency region and used in a different control dependency region. Other embodiments are described and claimed.
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公开(公告)号：US20180260559A1
公开(公告)日：2018-09-13
申请号：US15974749
申请日：2018-05-09
Applicant: International Business Machines Corporation
Inventor： AYMAN JARROUS , Dov Murik , Omer-Yehuda Boehm , Nitzan Peleg
CPC classification number: G06F21/54 , G06F8/433 , G06F8/447 , G06F8/54 , G06F9/44521 , G06F9/45516 , G06F9/4552 , G06F2221/033
Abstract: A method, computer program product, and computer system are provided. A processor receives an executable file for execution by an operating system, where the executable file includes a plurality of sections in a first order. A processor determines a second order that indicates a loading order for the plurality of sections, where the second order is distinct from the first order. A processor loads the plurality of sections of the executable file into a plurality of locations in memory of a device based on the second order. A processor resolves one or more memory references for the plurality of sections based on the plurality of locations in memory. A processor executes the plurality of sections of the executable file in the plurality of locations in memory.
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公开(公告)号：US20180253339A1
公开(公告)日：2018-09-06
申请号：US15938023
申请日：2018-03-28
Applicant: International Business Machines Corporation
Inventor： Eric L. Barsness , Daniel E. Beuch , Michael J. Branson , John M. Santosuosso
CPC classification number: G06F9/5083 , G06F8/36 , G06F8/433 , G06F9/50 , G06F16/9024 , G06F2209/5011
Abstract: Disclosed aspects relate to operation efficiency management in a shared pool of configurable computing resources. A first set of processing operations of a first application may be detected. A second set of processing operations of a second application may be detected. The first set of processing operations of the first application may be compared with the second set of processing operations of the second application. A substantial match of the first and second processing operations of the first and second applications may be determined. A single set of processing operations for both the first and second applications may be compiled.
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64.发明申请公开(公告)号：US20180253287A1
公开(公告)日：2018-09-06
申请号：US15582563
申请日：2017-04-28
Applicant: Jian Wang , Zhenqiang Yu , Yan Cheng
Inventor： Jian Wang , Zhenqiang Yu , Yan Cheng
CPC classification number: G06F8/447 , G06F8/24 , G06F8/315 , G06F8/433 , G06F8/51 , G06F8/53 , G06F9/44505 , G06F9/4488
Abstract: The method for translation of assembler computer language to validated object-oriented programming language converts Assembler Language Code (ALC) logical processes to equivalent object-oriented processes. The method uses various iteratively updated rules sets and graphical analysis tools to automate the translation process. The method further uses a Technical Rule Language (TRL) as an intermediate scripting language to map ALC sequential instruction sets to simplified Java constructs, which are verified and then translated to Java executable code.
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65.发明申请公开(公告)号：US20180210815A1
公开(公告)日：2018-07-26
申请号：US15412053
申请日：2017-01-23
Applicant: International Business Machines Corporation
Inventor： Kwan Yin Andrew Chau , Smitha Lal , Stephen Pham
CPC classification number: G06F11/3664 , G06F8/433 , G06F9/451 , G06F17/2247
Abstract: A method, apparatus, and computer program product to improve testing of web interfaces where each page and point of interaction in the web interfaces are represented by Page Objects. Responsive to a processor receiving code to navigate a path from a first Page Object to a second Page Object in the user interface, the path is identified as a slow path. Responsive to identifying the path as a slow path, a marker is displayed with the code.
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Patent Agency Ranking
公开(公告)号：US20180173508A1
公开(公告)日：2018-06-21
申请号：US15898844
申请日：2018-02-19
Applicant: International Business Machines Corporation
Inventor： FREDERIC CHANSON , SANIYA BEN HASSEN , MARC P. YVON
IPC: G06F8/41
CPC classification number: G06F8/41 , G06F8/433 , G06F8/4452
Abstract: A computer-implemented method for generating code for real-time stream processing, where data is streamed in tuples. One or more processors receive source code which includes code to be applied in a sequential series to one or more tuples. Processor(s) generate the code for real-time stream processing by: buffering received time sequence tuples in a buffer; and converting the code to be sequentially applied to the one or more tuples into code for buffered tuples with a loop construct. Processor(s) also generate code for: checking that all tuples in a processing window have been buffered; and applying the converted code to each tuple in the processing window.
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公开(公告)号：US20180137010A1
公开(公告)日：2018-05-17
申请号：US15349767
申请日：2016-11-11
Applicant: SAP SE
Inventor： Martin Mayer , Ulrich Auer , Arne Harren , Volker Driesen
CPC classification number: G06F11/1451 , G06F8/433 , G06F16/211 , G06F16/2343 , G06F16/2358 , G06F2201/80
Abstract: In an example embodiment, one or more changes to one or more objects in the software object database are received from a developer. A change list is generated based on the one or more changes. An object definition is exported for every object in the change list from a first schema in the database to a second schema in the software object database. A first object in the second schema is activated by mapping a logical schema name specified in the object definition for the first object to a corresponding physical schema name and creating or altering the first object in the second schema using the physical schema name.
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公开(公告)号：US09946536B2
公开(公告)日：2018-04-17
申请号：US14957629
申请日：2015-12-03
Applicant: International Business Machines Corporation
Inventor： Aharon Abadi , Moria Abadi
Abstract: Computer implemented method of refactoring JavaScript code for multi-threading concurrent execution, comprising: 1) Designating a source code which includes background code entries indicated by a user as executed in background. 2) Analyzing the source code entries to create a dependency record. 3) Creating a background process comprising the background code entries and removing code entries which read or write from DOM(s). 4) Creating a handler code comprising the write code entries. 5) Creating main code which includes: (a) Remaining code entries not included in the background process and the handler code. (b) Process initiation code initiating the background process. The process initiation code is placed at a process initiation point identified based on the dependency record which follows the read code entries in the source code execution path and precedes the write code entries. 6) Outputting refactored code file(s) which include the background process, handler code and main code.
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公开(公告)号：US09946522B1
公开(公告)日：2018-04-17
申请号：US15381236
申请日：2016-12-16
Applicant: International Business Machines Corporation
Inventor： Frederic Chanson , Saniya Ben Hassen , Marc P. Yvon
IPC: G06F9/45
CPC classification number: G06F8/41 , G06F8/433 , G06F8/4452
Abstract: A computer-implemented method for generating code for real-time stream processing, where data is streamed in tuples, and where each tuple has a timestamp and a value. One or more processors receive source code. The source code includes: code to be applied in a sequential series to one or more tuples; a definition of a size of a sequence of tuples to be processed as a processing window; and a size of a sequence of earlier tuples that a current tuple depends upon as a dependence window. Processor(s) generate the code for real-time stream processing by: buffering received time sequence tuples in a buffer in accordance with the processing window and the dependence window; and converting the code to be sequentially applied to the one or more tuples into code for buffered tuples with a loop construct.
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公开(公告)号：US20180088916A1
公开(公告)日：2018-03-29
申请号：US15278091
申请日：2016-09-28
Applicant: INTEL CORPORATION
Inventor： Sara S. Baghsorkhi , Christos Margiolas
IPC: G06F9/45
Abstract: In one example, a system for modifying applications to support incremental checkpoints can include logic to generate a dominator tree based on a control flow graph for source code, wherein the control flow graph and the dominator tree comprise a plurality of nodes corresponding to basic blocks of the source code. The processor can select a region based on a leaf node of the dominator tree, the region based on an instruction threshold, and insert a first set of commit instructions into the source code based on entry points into the region and insert a second set of commit instructions into the source code based on exit points from the region. The processor can update the dominator tree to exclude the selected region and compile the source code into an executable application, wherein the first set of commit instructions and the second set of commit instructions enable incremental checkpoints.
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