公开(公告)号：US10025570B2

公开(公告)日：2018-07-17

申请号：US15278091

申请日：2016-09-28

Applicant: INTEL CORPORATION

Inventor： Sara S. Baghsorkhi ,  Christos Margiolas

IPC: G06F9/45 ,  G06F8/41

Abstract: In one example, a system for modifying applications to support incremental checkpoints can include logic to generate a dominator tree based on a control flow graph for source code, wherein the control flow graph and the dominator tree comprise a plurality of nodes corresponding to basic blocks of the source code. The processor can select a region based on a leaf node of the dominator tree, the region based on an instruction threshold, and insert a first set of commit instructions into the source code based on entry points into the region and insert a second set of commit instructions into the source code based on exit points from the region. The processor can update the dominator tree to exclude the selected region and compile the source code into an executable application, wherein the first set of commit instructions and the second set of commit instructions enable incremental checkpoints.

公开(公告)号：US10409603B2

公开(公告)日：2019-09-10

申请号：US15396177

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Sara S. Baghsorkhi ,  Christos Margiolas

IPC: G06F9/30 ,  G06F12/10 ,  G06F12/1009 ,  G06F12/1027 ,  G06F9/38 ,  G06F15/76 ,  G06F3/06

Abstract: A processor of an aspect includes a decode unit to decode an instruction. The instruction is to indicate a source memory address information, and is to indicate a destination architecturally-visible storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to store a result in the destination architecturally-visible storage location. The result to indicate whether a logical memory address corresponding to the source memory address information is in a persistent memory. Other processors, methods, systems, and instructions are disclosed.

公开(公告)号：US20180189062A1

公开(公告)日：2018-07-05

申请号：US15396177

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Sara S. Baghsorkhi ,  Christos Margiolas

IPC: G06F9/30 ,  G06F12/1009 ,  G06F12/1027

CPC classification number: G06F9/3016 ,  G06F3/06 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30058 ,  G06F9/30101 ,  G06F9/3885 ,  G06F9/3889 ,  G06F9/3891 ,  G06F12/1009 ,  G06F12/1027 ,  G06F15/76 ,  G06F2212/205 ,  G06F2212/502

Abstract: A processor of an aspect includes a decode unit to decode an instruction. The instruction is to indicate a source memory address information, and is to indicate a destination architecturally-visible storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to store a result in the destination architecturally-visible storage location. The result to indicate whether a logical memory address corresponding to the source memory address information is in a persistent memory. Other processors, methods, systems, and instructions are disclosed.

公开(公告)号：US20180088916A1

公开(公告)日：2018-03-29

申请号：US15278091

申请日：2016-09-28

Applicant: INTEL CORPORATION

Inventor： Sara S. Baghsorkhi ,  Christos Margiolas

IPC: G06F9/45

CPC classification number: G06F8/433 ,  G06F11/07

Abstract: In one example, a system for modifying applications to support incremental checkpoints can include logic to generate a dominator tree based on a control flow graph for source code, wherein the control flow graph and the dominator tree comprise a plurality of nodes corresponding to basic blocks of the source code. The processor can select a region based on a leaf node of the dominator tree, the region based on an instruction threshold, and insert a first set of commit instructions into the source code based on entry points into the region and insert a second set of commit instructions into the source code based on exit points from the region. The processor can update the dominator tree to exclude the selected region and compile the source code into an executable application, wherein the first set of commit instructions and the second set of commit instructions enable incremental checkpoints.