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    Memory system with latency distribution optimization and an operating method thereof
    62.
    发明授权
    Memory system with latency distribution optimization and an operating method thereof 有权

    公开(公告)号：US11169712B2

    公开(公告)日：2021-11-09

    申请号：US16572476

    申请日：2019-09-16

    Applicant: SK hynix Inc.

    Inventor： Young Tack Jin ,  Sungjoon Ahn ,  Seong Won Shin

    IPC: G06F3/06 ,  G06F13/42 ,  G06F13/16 ,  G06F13/24

    Abstract: A memory system and an operating method thereof include: at least a CPU including multiple CPU cores, wherein the multiple CPU cores include reserved CPU cores and host CPU cores; at least a PCIe link coupled with the CPU, wherein the PCIe link includes at least a PCIe switch and a plurality of memory devices; and the plurality of memory devices coupled with the host CPU cores through respective workload threads and interrupt handlers, wherein the workload threads and interrupt handlers of each of the host CPU cores are configured to be optimized, the host CPU cores are isolated for the optimized workloads threads and interrupt handlers, and the workload threads and interrupt handlers are executed at the host CPU cores coupled thereto.

    Information processor with tightly coupled smart memory unit
    63.
    发明授权
    Information processor with tightly coupled smart memory unit 有权

    公开(公告)号：US11163710B2

    公开(公告)日：2021-11-02

    申请号：US16773344

    申请日：2020-01-27

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Shyh-An Chi

    IPC: G06F13/28 ,  G06F13/24 ,  G06F12/1081 ,  G06F13/32 ,  G06F15/78 ,  G06F13/40

    Abstract: A processor includes a plurality of first processing units. The processor further includes a direct memory access unit coupled to a first processing unit of the plurality of first processing units. The processor further includes a data storage unit. The processor further includes a second processing unit adapted to process data transferred from the data storage unit, wherein the direct memory access unit is configured to transfer data stored in a memory to the data storage unit, the second processing unit is separate from the plurality of first processing units and the direct memory access unit, and the first processing unit of the plurality of first processing units and the second processing unit are configured to work in parallel. The processor further includes a first register configured to store data corresponding to an interrupt request related to the second processing unit or the data storage unit.

    DIRECTED INTERRUPT FOR MULTILEVEL VIRTUALIZATION
    64.
    发明申请
    DIRECTED INTERRUPT FOR MULTILEVEL VIRTUALIZATION 有权

    公开(公告)号：US20210318973A1

    公开(公告)日：2021-10-14

    申请号：US17358172

    申请日：2021-06-25

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Bernd Nerz ,  Marco Kraemer ,  Christoph Raisch ,  Donald William Schmidt ,  Peter Dana Driever

    IPC: G06F13/24 ,  G06F9/54

    Abstract: An interrupt signal is provided to a first guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is scheduled for usage by the guest operating system. If the target processor is not scheduled for usage, the bus attachment device forwards the interrupt signal using broadcasting and updates a forwarding vector entry stored in a memory section assigned to a second guest operating system hosting the first guest operating system. The update is used for indicating to the first operating system that there is a first interrupt signal addressed to the interrupt target ID to be handled.

    ENHANCED DIRECTED SYSTEM MANAGEMENT INTERRUPT MECHANISM
    65.
    发明申请
    ENHANCED DIRECTED SYSTEM MANAGEMENT INTERRUPT MECHANISM 有权

    公开(公告)号：US20210318971A1

    公开(公告)日：2021-10-14

    申请号：US17208336

    申请日：2021-03-22

    Applicant: Intel Corporation

    Inventor： Gaurav Khanna ,  Prashant Sethi ,  Venkatesh Ramamurthy

    IPC: G06F13/24

    Abstract: An example compute node is disclosed that includes a plurality of processor cores. The example further includes an operating system (OS) having an OS power management (OSPM) engine to determine that a first of the plurality of processor cores has entered an idle state; and a system management mode (SMM) handler to detect a system management interrupt (SMI) and transition control of hardware resources of the first processor core from the OS to a basic input output system (BIOS) to enter a system management mode (SMM) in order to perform one or more platform management operations.

    System and method to reduce host interrupts for non-critical errors
    67.
    发明授权
    System and method to reduce host interrupts for non-critical errors 有权

    公开(公告)号：US11132314B2

    公开(公告)日：2021-09-28

    申请号：US16798744

    申请日：2020-02-24

    Applicant: DELL PRODUCTS, LP

    Inventor： Akkiah Maddukuri ,  Arun Muthaiyan ,  Jordan Chin ,  Timothy M. Lambert ,  Nasiha Hrustemovic

    IPC: G06F13/24 ,  G06F11/07

    Abstract: An information handling system includes a device, a processor, and a runtime agent. the device provides a System Management Interrupt (SMI) in response to an error on the device. The processor receives the SMI, enters a System Management Mode (SMM), and executes first interrupt handler code in SMM to provide interrupt information associated with the SMI when the SMI is associated with a non-critical error on the device, and exit SMM to a runtime mode. The runtime agent receives the interrupt information during the runtime mode to execute second interrupt handler code to service the non-critical error on the device.

    Distributed fairness protocol for interconnect networks
    68.
    发明授权
    Distributed fairness protocol for interconnect networks 有权

    公开(公告)号：US11126577B2

    公开(公告)日：2021-09-21

    申请号：US16678199

    申请日：2019-11-08

    Applicant: Oracle International Corporation

    Inventor： Robert Golla ,  Manish Shah ,  Mark Luttrell

    IPC: G06F13/36 ,  G06F13/24 ,  G06F13/40

    Abstract: A system is disclosed, including a plurality of access units, a plurality of circuit nodes each coupled to a respective access unit, and a plurality of data processing nodes each coupled to a respective access unit. A particular data processing node may be configured to generate a plurality of data transactions. The particular data processing node may also be configured to determine an availability of a coupled access unit. In response to a determination that the coupled access unit is unavailable, the particular data processing node may be configured to halt a transfer of the plurality of data transactions to the coupled access unit and assert a halt indicator signal. In response to a determination that the coupled access unit is available, the particular data processing node may be configured to transfer the particular data transaction to the coupled access unit.

    Electronic device for scheduling a plurality of tasks and operating method thereof
    70.
    发明授权
    Electronic device for scheduling a plurality of tasks and operating method thereof 有权

    公开(公告)号：US11113215B2

    公开(公告)日：2021-09-07

    申请号：US16698430

    申请日：2019-11-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngmin Oh ,  Kibeom Kim ,  Sangho Lee ,  Yeona Hong ,  Gajin Song

    IPC: G06F13/24 ,  G06F9/38 ,  G06F9/48 ,  G06Q10/06

    Abstract: An electronic device which schedules a plurality of tasks, and an operating method thereof. The electronic device includes a processor and a memory operatively connected to the processor, and when being executed, the memory stores instructions that cause the processor to: detect occurrence of an interrupt requesting performance of a second task while performing a first task; obtain reference values according to a time of the first task, and reference values according to a time of the second task; schedule the first task and the second task based on a reference value of the first task and a reference value of the second task which correspond to a time at which the interrupt occurs; and process the first task and the second task based on a result of the scheduling. Other embodiments are possible.

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