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    Hybrid lookahead branch target cache
    1.
    发明授权
    Hybrid lookahead branch target cache 有权

    公开(公告)号：US10747540B2

    公开(公告)日：2020-08-18

    申请号：US15340106

    申请日：2016-11-01

    Applicant: Oracle International Corporation

    Inventor： Yuan Chou ,  Manish Shah

    IPC: G06F9/38

    Abstract: An apparatus is disclosed, the apparatus including a branch target cache memory configured to store one or more entries. Each entry of the one or more entries may include an address tag and a corresponding target address. The apparatus may also include a control circuit configured to check for at least one taken branch instruction in a group of one or more instructions fetched using a current address. The control circuit may be further configured to generate an address tag corresponding to the group of one or more instructions using another address used prior to the current address in response to a determination that the group of one or more instructions includes a taken branch instruction. In addition, the control circuit may be configured to store the corresponding address tag and a target address associated with the taken branch instruction in a particular entry in the branch target cache memory.

    Distributed fairness protocol for interconnect networks
    3.
    发明授权
    Distributed fairness protocol for interconnect networks 有权

    公开(公告)号：US10474601B2

    公开(公告)日：2019-11-12

    申请号：US15425025

    申请日：2017-02-06

    Applicant: Oracle International Corporation

    Inventor： Robert Golla ,  Manish Shah ,  Mark Luttrell

    IPC: G06F13/36 ,  G06F13/24 ,  G06F13/40

    Abstract: A system is disclosed, including a plurality of access units, a plurality of circuit nodes each coupled to a respective access unit, and a plurality of data processing nodes each coupled to a respective access unit. A particular data processing node may be configured to generate a plurality of data transactions. The particular data processing node may also be configured to determine an availability of a coupled access unit. In response to a determination that the coupled access unit is unavailable, the particular data processing node may be configured to halt a transfer of the plurality of data transactions to the coupled access unit and assert a halt indicator signal. In response to a determination that the coupled access unit is available, the particular data processing node may be configured to transfer the particular data transaction to the coupled access unit.

    Method and apparatus for augmentation and disambiguation of branch history in pipelined branch predictors
    5.
    发明授权
    Method and apparatus for augmentation and disambiguation of branch history in pipelined branch predictors 有权

    公开(公告)号：US10318303B2

    公开(公告)日：2019-06-11

    申请号：US15471001

    申请日：2017-03-28

    Applicant: Oracle International Corporation

    Inventor： Manish Shah ,  Jared Smolens

    IPC: G06F9/42 ,  G06F9/32 ,  G06F12/02 ,  G06F9/38 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/0864

    Abstract: A method and apparatus for performing branch prediction is disclosed. A branch predictor includes a history buffer configured to store a branch history table indicative of a history of a plurality of previously fetched branch instructions. The branch predictor also includes a branch target cache (BTC) configured to store branch target addresses for fetch addresses that have been identified as including branch instructions but have not yet been predicted. A hash circuit is configured to form a hash of a fetch address, history information received from the history buffer, and hit information received from the BTC, wherein the fetch address includes a branch instruction. A branch prediction unit (BPU) configured to generate a branch prediction for the branch instruction included in the fetch address based on the hash formed from the fetch address, history information, and BTC hit information.

    Processing instruction control transfer instructions
    6.
    发明授权
    Processing instruction control transfer instructions 有权

    公开(公告)号：US10198260B2

    公开(公告)日：2019-02-05

    申请号：US14994796

    申请日：2016-01-13

    Applicant: Oracle International Corporation

    Inventor： Manish Shah ,  Christopher Olson

    IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32

    Abstract: A system that for storing program counter values is disclosed. The system may include a program counter, a first memory including a plurality of sectors, a first circuit configured to retrieve a program instruction from a location in memory dependent upon a value of the program counter, send the value of the program counter to an array for storage and determination a predicted outcome of the program instruction in response to a determination that execution of the program instruction changes a program flow. The second circuit may be configured to retrieve the value of the program counter from a given entry in a particular sector of the array, and determine an actual outcome of the program instruction dependent upon the retrieved value of the program counter.

    DISTRIBUTED FAIRNESS PROTOCOL FOR INTERCONNECT NETWORKS
    7.
    发明申请
    DISTRIBUTED FAIRNESS PROTOCOL FOR INTERCONNECT NETWORKS 审中-公开

    公开(公告)号：US20180225239A1

    公开(公告)日：2018-08-09

    申请号：US15425025

    申请日：2017-02-06

    Applicant: Oracle International Corporation

    Inventor： Robert Golla ,  Manish Shah ,  Mark Luttrell

    IPC: G06F13/36 ,  G06F13/24 ,  G06F13/40

    CPC classification number: G06F13/36 ,  G06F13/24 ,  G06F13/4068

    Abstract: A system is disclosed, including a plurality of access units, a plurality of circuit nodes each coupled to a respective access unit, and a plurality of data processing nodes each coupled to a respective access unit. A particular data processing node may be configured to generate a plurality of data transactions. The particular data processing node may also be configured to determine an availability of a coupled access unit. In response to a determination that the coupled access unit is unavailable, the particular data processing node may be configured to halt a transfer of the plurality of data transactions to the coupled access unit and assert a halt indicator signal. In response to a determination that the coupled access unit is available, the particular data processing node may be configured to transfer the particular data transaction to the coupled access unit.

    METHOD FOR REDUCING FETCH CYCLES FOR RETURN-TYPE INSTRUCTIONS
    8.
    发明申请
    METHOD FOR REDUCING FETCH CYCLES FOR RETURN-TYPE INSTRUCTIONS 审中-公开

    公开(公告)号：US20180060075A1

    公开(公告)日：2018-03-01

    申请号：US15254648

    申请日：2016-09-01

    Applicant: Oracle International Corporation

    Inventor： Yuan Chou ,  Manish Shah ,  Richa Aggarwal

    IPC: G06F9/38

    CPC classification number: G06F9/3806 ,  G06F9/3844

    Abstract: An apparatus is disclosed, the apparatus including a branch target cache configured to store one or more branch addresses, a memory configured to store a return target stack, and a circuit. The circuit may be configured to determine, for a group of one or more fetched instructions, a prediction value indicative of whether the group includes a return instruction. In response to the prediction value indicating that the group includes a return instruction, the circuit may be further configured to select a return address from the return target stack. The circuit may also be configured to determine a hit or miss indication in the branch target cache for the group, and to, in response to receiving a miss indication from the branch target cache, select the return address as a target address for the return instruction.

    Power Reduction for Fully Associated Translation Lookaside Buffer
    9.
    发明申请
    Power Reduction for Fully Associated Translation Lookaside Buffer 有权
    完全相关的翻译后备缓冲区的功率降低

    公开(公告)号：US20150213153A1

    公开(公告)日：2015-07-30

    申请号：US14163096

    申请日：2014-01-24

    Applicant: ORACLE INTERNATIONAL CORPORATION

    Inventor： Manish Shah ,  Gideon Levinsky

    IPC: G06F17/30 ,  G06F12/10 ,  G11C15/00

    CPC classification number: G06F17/30982 ,  G06F12/1036 ,  G06F12/1054 ,  G06F2212/1028 ,  G06F2212/301 ,  G06F2212/684 ,  G11C15/00 ,  Y02D10/13

    Abstract: An apparatus and method for saving power during TLB searches is disclosed. In one embodiment, a TLB includes a CAM having a plurality of entries each storing a virtual address, and enable logic coupled to the CAM. Responsive to initiation of a TLB query by a thread executing on a processor that includes the TLB, the enable logic is configured to enable only those CAM entries that are associated with the initiating thread. Entries in the CAM not associated with the thread are not enabled. Accordingly, an initial search of the TLB for responsive to the query is conducted only in the CAM entries that are associated with the thread. Those CAM entries that are not associated with the thread are not searched. As a result, dynamic power consumption during TLB searches may be reduced.

    Abstract translation: 公开了一种在TLB搜索中节省电力的装置和方法。 在一个实施例中，TLB包括具有多个条目的CAM，每个条目存储虚拟地址，并且使能耦合到CAM的逻辑。 响应于在包括TLB的处理器上执行的线程启动TLB查询，启用逻辑被配置为仅启用与启动线程相关联的那些CAM条目。 未与线程相关联的CAM中的条目未启用。 因此，仅在与线程相关联的CAM条目中进行用于响应于查询的TLB的初始搜索。 不搜索与线程无关的那些CAM条目。 因此，TLB搜索中的动态功耗可能会降低。

    Method for reducing fetch cycles for return-type instructions
    10.
    发明授权
    Method for reducing fetch cycles for return-type instructions 有权

    公开(公告)号：US11099849B2

    公开(公告)日：2021-08-24

    申请号：US15254648

    申请日：2016-09-01

    Applicant: Oracle International Corporation

    Inventor： Yuan Chou ,  Manish Shah ,  Richa Aggarwal

    IPC: G06F9/38

    Abstract: An apparatus includes a branch target cache configured to store one or more branch addresses, a memory configured to store a return target stack, and a circuit. The circuit may be configured to determine, for a group of one or more fetched instructions, a prediction value indicative of whether the group includes a return instruction. In response to the prediction value indicating that the group includes a return instruction, the circuit may be further configured to select a return address from the return target stack. The circuit may also be configured to determine a hit or miss indication in the branch target cache for the group, and to, in response to receiving a miss indication from the branch target cache, select the return address as a target address for the return instruction.

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