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公开(公告)号：US20070073981A1
公开(公告)日：2007-03-29
申请号：US11528970
申请日：2006-09-27
Applicant: Jae-Hyuk Im , Chang-Ho Do
Inventor： Jae-Hyuk Im , Chang-Ho Do
IPC: G06F12/00
CPC classification number: G11C7/1075 , G11C8/12 , G11C8/16 , G11C2207/107
Abstract: A multi-port memory device includes a plurality of ports located at a center region of the multi-port memory device, each for performing a data communication with a corresponding external device; a plurality of banks arranged at upper and lower regions of the multi-port memory device in a row direction on the basis of the plurality of ports; and first and second global I/O data buses arranged in the row direction between the banks and the ports, each for independently performing a data transmission between the banks and the ports.
Abstract translation: 多端口存储器件包括多个端口，位于多端口存储器件的中心区域，每个端口用于执行与对应的外部设备的数据通信; 基于多个端口，在多个端口存储器件的上部和下部区域中的行方向上布置多个存储体; 以及在行和端口之间沿行方向布置的第一和第二全局I / O数据总线，每个用于独立地执行存储体和端口之间的数据传输。
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公开(公告)号：US20070070725A1
公开(公告)日：2007-03-29
申请号：US11528968
申请日：2006-09-27
Applicant: Chang-Ho Do
Inventor： Chang-Ho Do
IPC: G11C5/14
Abstract: An internal voltage supplying device includes a level sensing means for sensing a level of a high voltage with respect to a core voltage, an oscillation signal generating means for generating an oscillation signal controlled by the level sensing means, and a pumping means for pumping charges during an activation interval of the oscillation signal to generate the high voltage having a level higher than a level of the core voltage, by a level of a threshold voltage or higher.
Abstract translation: 内部电压供给装置包括用于感测相对于核心电压的高电压电平的电平检测装置，用于产生由电平感测装置控制的振荡信号的振荡信号产生装置，以及用于在 振荡信号的激活间隔，以产生具有高于核心电压电平的电平的高电压或阈值电压或更高的电平。
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公开(公告)号：US20060140038A1
公开(公告)日：2006-06-29
申请号：US11139181
申请日：2005-05-27
Applicant: Chang-Ho Do
Inventor： Chang-Ho Do
IPC: G11C5/14
CPC classification number: G11C5/145
Abstract: An internal voltage generator for use in a semiconductor memory device, includes: an internal voltage generation unit for generating an internal voltage by performing a charge pumping operation to a power supply voltage based on a result of comparing the internal voltage with a reference voltage; and an initial internal voltage generation unit for supplying the power supply voltage as the internal voltage based on a result of comparing the internal voltage with the power supply voltage when an operating voltage supplied to the semiconductor memory device is lower than a predetermined voltage level.
Abstract translation: 一种用于半导体存储器件的内部电压发生器，包括：内部电压产生单元，用于通过基于将内部电压与参考电压进行比较的结果对电源电压进行电荷泵送操作来产生内部电压; 以及初始内部电压产生单元，用于当提供给半导体存储器件的工作电压低于预定电压电平时，基于将内部电压与电源电压进行比较的结果来提供电源电压作为内部电压。
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公开(公告)号：US07068547B2
公开(公告)日：2006-06-27
申请号：US10792065
申请日：2004-03-02
Applicant: Chang-Ho Do
Inventor： Chang-Ho Do
IPC: G11C7/00
CPC classification number: G11C5/147
Abstract: An internal voltage generating circuit in a semiconductor memory device includes a comparing unit for comparing a voltage level of an internal voltage with that of a reference voltage, a pull-up driving unit for performing a pull-up operation for an output terminal in response to an output signal of the comparing unit, and a discharging unit for discharging the output terminal in a period of which the voltage level of the internal voltage is higher than a predetermined target voltage level.
Abstract translation: 半导体存储器件中的内部电压产生电路包括用于将内部电压的电压电平与参考电压的电压电平进行比较的比较单元，用于对输出端子执行上拉操作的上拉驱动单元响应于 比较单元的输出信号，以及用于在内部电压的电压高于预定的目标电压电平的期间对输出端子进行放电的放电单元。
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公开(公告)号：US20060041804A1
公开(公告)日：2006-02-23
申请号：US11024376
申请日：2004-12-27
Applicant: Chang-Ho Do
Inventor： Chang-Ho Do
IPC: G01R31/28
CPC classification number: G11C29/12 , G11C11/401 , G11C29/12005 , G11C2029/1204
Abstract: A semiconductor memory device for performing a reliability test includes a write driving block for generating a predetermined test voltage in a test mode and delivering a data inputted from an external circuit into the local I/O line pair during a data access operation in a normal mode, a local I/O line pair coupled to the write driving block for receiving the predetermined test voltage in the test mode, and a cell array having a plurality of unit cells and a plurality of bit line pairs respectively having first and second bit lines and coupled to at least one unit cell for receiving the predetermined test voltage from each local I/O line pair to thereby check a result of the reliability test in the test mode.
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Patent Agency Ranking
公开(公告)号：US06961270B2
公开(公告)日：2005-11-01
申请号：US10792064
申请日：2004-03-02
Applicant: Chang-Ho Do
Inventor： Chang-Ho Do
IPC: G11C11/413 , G11C5/00 , G11C5/14 , G11C7/00 , G11C11/4072 , H03K17/22
CPC classification number: G11C5/14
Abstract: A power-up circuit includes a power supply voltage level follower unit for outputting a first bias voltage and a second bias voltage which increase or decrease in proportion to a power supply voltage; a first power supply voltage detecting unit for detecting a first critical voltage level where a logic level of a power-up signal is changed in response to the first bias voltage when the power supply voltage decreases; a second power supply voltage detecting unit for detecting a second critical voltage level where a logic level of the power-up signal is changed in response to the second bias voltage when the power supply voltage increases; and a trigger unit for inverting an output signal of the trigger unit in response to one of a first detect signal outputted from the first power supply voltage detecting unit when the power supply voltage decreases and a second detect signal outputted from the second power supply voltage detecting unit when the power supply voltage increases, wherein the second critical voltage level is higher than the first critical voltage level.
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公开(公告)号：US06950357B2
公开(公告)日：2005-09-27
申请号：US10835709
申请日：2004-04-29
Applicant: Chang-Ho Do
Inventor： Chang-Ho Do
CPC classification number: G11C29/46
Abstract: A test mode flag signal generator for use in a semiconductor memory device includes a test mode decoder for generating M numbers of test mode flag signals; and an auxiliary test mode flag signal generating means for generating M×2N numbers of test mode flag signals by using N numbers of external signals and the M numbers of test mode flag signals.
Abstract translation: 一种用于半导体存储器件的测试模式标志信号发生器包括一个产生M个测试模式标志信号的测试模式解码器; 以及辅助测试模式标志信号产生装置，用于通过使用N个外部信号和M个测试模式标志信号来产生测试模式标志信号的M×N×N个数量。
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公开(公告)号：US20050140405A1
公开(公告)日：2005-06-30
申请号：US10788683
申请日：2004-02-27
Applicant: Chang-Ho Do , Jae-Jin Lee
Inventor： Chang-Ho Do , Jae-Jin Lee
IPC: G11C7/00 , G11C7/20 , G11C11/4072 , H03K17/22 , H03L7/00
CPC classification number: H03K17/223
Abstract: A power-up circuit includes a power supply voltage level follower unit for outputting a first bias voltage and a second bias voltage which increase or decrease in proportion to a power supply voltage; a first power supply voltage detecting unit for detecting that the power supply voltage becomes a first critical voltage level of the power supply voltage corresponding to a threshold voltage of an NMOS transistor in response to the first bias voltage; a second power supply voltage detecting unit for detecting that the power supply voltage becomes a second critical voltage level of the power supply voltage corresponding to a threshold voltage of a PMOS transistor in response to the second bias voltage; and a summation unit for performing a logic operation to a first detect signal outputted from the first power supply voltage detecting unit and a second detect signal outputted from the second power supply voltage detecting unit to thereby output a confirmation signal, wherein the confirmation signal is activated when the power supply voltage satisfies both of the first and second critical voltage levels.
Abstract translation: 上电电路包括用于输出与电源电压成比例地增加或减小的第一偏置电压和第二偏置电压的电源电压电平跟随器单元; 第一电源电压检测单元，用于响应于所述第一偏置电压检测所述电源电压变为对应于NMOS晶体管的阈值电压的电源电压的第一临界电压电平; 第二电源电压检测单元，用于响应于所述第二偏置电压检测所述电源电压变为对应于PMOS晶体管的阈值电压的电源电压的第二临界电压电平; 以及求和单元，用于对从第一电源电压检测单元输出的第一检测信号和从第二电源电压检测单元输出的第二检测信号执行逻辑运算，从而输出确认信号，其中确认信号被激活 当电源电压满足第一和第二临界电压电平时。
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公开(公告)号：US08842486B2
公开(公告)日：2014-09-23
申请号：US13329688
申请日：2011-12-19
Applicant: Chang-Ho Do
Inventor： Chang-Ho Do
CPC classification number: G11C29/1201 , G11C29/40 , G11C29/44 , G11C29/48 , G11C2029/5002
Abstract: An integrated circuit chip includes an internal circuit configured to generate output data, an inversion determination unit configured to activate/deactivate an inversion signal according to state information regarding a state of the integrate circuit chip, and a signal output circuit configured to invert or not to invert the output data in response to the inversion signal and output the inverted or non-inverted output data.
Abstract translation: 集成电路芯片包括被配置为产生输出数据的内部电路，反转确定单元，被配置为根据关于集成电路芯片的状态的状态信息来激活/去激活反转信号;以及信号输出电路，被配置为反转或不反转 根据反相信号反转输出数据，并输出反相或非反相输出数据。
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80.发明申请SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE HAVING FUSE CIRCUIT 审中-公开具有保险丝电路的半导体集成电路和半导体存储器件公开(公告)号：US20120275244A1
公开(公告)日：2012-11-01
申请号：US13313370
申请日：2011-12-07
Applicant: Chang-Ho DO
Inventor： Chang-Ho DO
CPC classification number: G11C17/18 , G11C17/16 , G11C29/785
Abstract: A semiconductor integrated circuit includes: a fuse; a first driving unit configured to drive a sensing node in response to a first fuse sensing signal; a second driving unit configured to drive the sensing node in response to a second fuse sensing signal, wherein the second driving unit and the fuse form a driving path; a bypass resistor unit connected in parallel with the fuse; and a sensing unit configured to sense a programming state of the fuse in response to a voltage of the sensing node.
Abstract translation: 半导体集成电路包括：保险丝; 第一驱动单元，被配置为响应于第一熔丝感测信号驱动感测节点; 第二驱动单元，被配置为响应于第二熔丝感测信号驱动感测节点，其中第二驱动单元和熔丝形成驱动路径; 与保险丝并联连接的旁路电阻器单元; 以及感测单元，被配置为响应于所述感测节点的电压感测所述保险丝的编程状态。
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