Apparatus and method for over-voltage and over-current protection for a step-up current-mode converter
    71.
    发明申请
    Apparatus and method for over-voltage and over-current protection for a step-up current-mode converter 失效
    用于升压电流模式转换器的过电压和过电流保护的装置和方法

    公开(公告)号:US20060132997A1

    公开(公告)日:2006-06-22

    申请号:US11305237

    申请日:2005-12-19

    IPC分类号: H02H3/42

    摘要: In an apparatus for over-voltage and over-current protection for a step-up current-mode converter including an inductor connected via a phase node to a switch that is switched by a control signal to convert an input voltage to an output voltage, a controller has a multiplexed pin, and a resistor and a capacitor are connected in parallel between the multiplexed pin and the phase node. In an over-voltage protection mode, the controller senses the voltage on the multiplexed pin, and in an over-current protection mode, the controller supplies a current to flow through the resistor and senses the voltage on the multiplexed pin.

    摘要翻译: 在用于升压电流模式转换器的过电压和过电流保护的装置中,包括通过相位节点连接到通过控制信号切换以将输入电压转换为输出电压的开关的电感器, 控制器具有复用引脚,并且电阻器和电容器并联连接在多路复用引脚和相位节点之间。 在过电压保护模式下,控制器检测多路复用引脚上的电压,并且在过流保护模式下,控制器提供电流流过电阻并感测复用引脚上的电压。

    Single-chip common-drain JFET device and its applications
    72.
    发明申请
    Single-chip common-drain JFET device and its applications 失效
    单片共漏极JFET器件及其应用

    公开(公告)号:US20050285158A1

    公开(公告)日:2005-12-29

    申请号:US11165028

    申请日:2005-06-24

    摘要: A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

    摘要翻译: 单芯片公共漏极JFET器件包括漏极,两个栅极和两个源极,使得与其形成两个公共漏极JFET。 由于在单个芯片内合并的两个JFET,其间不需要引线接合连接,因此没有由接合线引起的寄生电感和电阻,因此提高性能并降低封装成本。 单片式公共漏极JFET器件可以应用于降压转换器,升压转换器,反相转换器,开关和两级DC-DC转换器,以提高其性能和效率。 还提供了用于电流感测或比例电流产生的替代单芯片公共漏极JFET器件。

    Current sense apparatus and method
    73.
    发明授权
    Current sense apparatus and method 失效
    电流检测装置及方法

    公开(公告)号:US06801030B2

    公开(公告)日:2004-10-05

    申请号:US10442084

    申请日:2003-05-21

    IPC分类号: G01R3300

    摘要: A current sense apparatus and method comprises a common drain DMOSFET and a MOSFET connected in series between a high voltage and a low voltage to serve as an output stage. The DMOSFET produces a phase output current, a mirror current mirrored from the phase output current, and a sense voltage. A servo amplifier is connected with the mirror current and sense voltage to produce a current sense signal. Due to the mirror current from the DMOSFET proportional to the phase output current, the current sense apparatus senses the phase output current in a temperature independent manner.

    摘要翻译: 电流检测装置和方法包括在高电压和低电压之间串联连接的公共漏极DMOSFET和MOSFET,用作输出级。 DMOSFET产生相输出电流,从相输出电流镜像的镜电流和感测电压。 伺服放大器与反射镜电流和感测电压连接,产生电流检测信号。 由于来自DMOSFET的反射电流与相输出电流成比例,电流检测装置以独立于温度的方式感测相输出电流。

    Trimmer method and device for circuits
    74.
    发明授权
    Trimmer method and device for circuits 失效
    微调方法和电路设备

    公开(公告)号:US06703885B1

    公开(公告)日:2004-03-09

    申请号:US10245390

    申请日:2002-09-18

    IPC分类号: H03L500

    CPC分类号: G05F1/56

    摘要: In a trimmer method and device, a reference signal of a target circuit is compared with a test signal, and a binary count output is generated according to result of the comparison. Thereafter, according to logic states of bits of the binary count output, electrical conduction through passive components that are coupled to the target circuit and that correspond respectively to the bits of the binary count output are selectively enabled and disabled so as to adjust the reference signal. The above steps are repeated by varying the binary count output until the reference signal approximates the test signal. Thereafter, fuses coupled to the passive components are melted selectively in a single fuse-melting operation so as to maintain the enabled and disabled states of electrical conduction through the passive components in order to set the reference signal to be approximate to the test signal.

    摘要翻译: 在微调方法和装置中,将目标电路的参考信号与测试信号进行比较,并根据比较结果生成二进制计数输出。 此后,根据二进制计数输出的位的逻辑状态,选择性地使能和禁止耦合到目标电路并且分别对应于二进制计数输出的位的无源分量的电传导,以便调整参考信号 。 通过改变二进制计数输出重复上述步骤,直到参考信号近似于测试信号。 此后,耦合到无源部件的熔丝在单熔丝熔化操作中选择性熔化,以便通过无源部件保持启用和禁用的导电状态,以将参考信号设置为接近测试信号。

    Multi-phase DC-to-DC buck converter with multi-phase current balance and adjustable load regulation
    75.
    发明授权
    Multi-phase DC-to-DC buck converter with multi-phase current balance and adjustable load regulation 失效
    多相DC-DC降压转换器,具有多相电流平衡和可调负载调节功能

    公开(公告)号:US06670794B1

    公开(公告)日:2003-12-30

    申请号:US10193119

    申请日:2002-07-12

    IPC分类号: G05F170

    CPC分类号: H02M3/1584

    摘要: To balance the current of individual channel as well as regulate the output voltage for a multi-phase DC-to-DC buck converter, the converter output voltage is sensed and compared with a reference signal to produce a first error signal serving as first control signal for PWM signals of the converter and the channel currents are sensed, summed, averaged and subtracted to produce second error signals that are further modified by saw-tooth wave signal to produce second control signals for the PWM signals. Moreover, the reference signal is controlled by the summed channel currents for adjustable load regulation.

    摘要翻译: 为了平衡单个通道的电流以及调节多相DC-DC降压转换器的输出电压,转换器输出电压被检测并与参考信号进行比较,以产生用作第一控制信号的第一误差信号 对于转换器的PWM信号和通道电流被感测,相加,平均和相减,以产生第二误差信号,其进一步被锯齿波信号修改以产生用于PWM信号的第二控制信号。 此外,参考信号由可调负载调节的总和通道电流控制。

    Recessed structure for shallow trench isolation and salicide process
    76.
    发明授权
    Recessed structure for shallow trench isolation and salicide process 失效
    浅沟槽隔离和自杀过程的嵌入式结构

    公开(公告)号:US5891771A

    公开(公告)日:1999-04-06

    申请号:US995339

    申请日:1997-12-22

    IPC分类号: H01L21/762 H01L21/76

    CPC分类号: H01L21/76232

    摘要: A shallow trench isolated FET LDD structure that has a low probability of short circuiting at the silicon to trench interface or between the source or drain and the gate (because of a titanium silicide bridge) is described. It is based on an isolation trench having a top portion with vertical sides and a lower portion with sloping sides. With the filled trench in place, along with a polysilicon gate and gate oxide, the thinner, lightly doped, N type layer is formed using ion implantation. Spacers are then formed on the gate but, prior to the second ion implant step, a few hundred Angstroms of silicon is selectively removed from the surface. This causes the trench filler material to extend above the wafer surface and the spacers to extend above the gate. A deeper, more strongly N-type, layer is then formed in the usual way, followed by the standard SALICIDE process for making contact to source, gate, and drain.

    摘要翻译: 描述了在硅到沟槽界面处或在源极或漏极与栅极之间(由于硅化钛桥)的短路概率较低的浅沟槽隔离FET LDD结构。 它基于具有垂直侧面的顶部和具有倾斜侧面的下部的隔离沟槽。 在填充沟槽就位的同时,与多晶硅栅极和栅极氧化物一起,使用离子注入形成较薄的轻掺杂N型层。 然后在栅极上形成间隔物,但是在第二离子注入步骤之前,从表面选择性地除去几百埃的硅。 这导致沟槽填充材料在晶片表面上方延伸并且间隔物在栅极上方延伸。 然后以通常的方式形成更深更强的N型层,接着形成与源极,栅极和漏极接触的标准SALICIDE工艺。

    Light emitting device current regulator circuit and control method thereof

    公开(公告)号:US09686829B2

    公开(公告)日:2017-06-20

    申请号:US13466705

    申请日:2012-05-08

    申请人: Jing-Meng Liu

    发明人: Jing-Meng Liu

    IPC分类号: H05B33/08

    CPC分类号: H05B33/0827

    摘要: A light emitting device current regulator circuit is disclosed. A light emitting device circuit has a first end for receiving light emitting device operation power, and a second end. The light emitting device current regulator circuit includes: an internal voltage generation circuit coupled to the second end, for generating an internal voltage according to a second end voltage to supply electrical power to the light emitting device current regulator circuit, wherein the supply voltage generation circuit includes a charge storage device for storing charges from the second end voltage to generate the supply voltage; and a current control circuit coupled to the second end, the current control circuit regulating the light emitting device current according to a control signal, wherein the control signal at least intermittently reduces the light emitting device current to zero or low current in order to raise the second end voltage.

    Analog photovoltaic power circuit with auto zero calibration
    78.
    发明授权
    Analog photovoltaic power circuit with auto zero calibration 有权
    具有自动零点校准功能的模拟光伏电源电路

    公开(公告)号:US09306443B2

    公开(公告)日:2016-04-05

    申请号:US14023900

    申请日:2013-09-11

    申请人: Jing-Meng Liu

    发明人: Jing-Meng Liu

    CPC分类号: H02M1/08 H02J3/385 Y02E10/58

    摘要: The invention provides an analog photovoltaic power circuit with auto zero calibration, which judges whether the current trend or voltage trend has the same direction as or different direction from the power trend, and adjusts an input/output power conversion accordingly, so that an input current approaches to an optimum current corresponding to a maximum power point, in which the judgments of the current trend, voltage trend and power trend is calibrated with auto-zero circuitry.

    摘要翻译: 本发明提供一种具有自动归零校准的模拟光伏电源电路,其判断当前趋势或电压趋势是否与电力趋势具有相同的方向或不同的方向,并且相应地调整输入/输出功率转换,使得输入电流 接近对应于最大功率点的最佳电流,其中使用自动归零电路校准当前趋势,电压趋势和功率趋势的判断。

    Backlight control circuit with flexible configuration
    79.
    发明授权
    Backlight control circuit with flexible configuration 有权
    背光控制电路配置灵活

    公开(公告)号:US09072137B2

    公开(公告)日:2015-06-30

    申请号:US12008798

    申请日:2008-01-14

    IPC分类号: G09G3/36 H05B33/08 G09G3/34

    摘要: The present invention discloses a backlight control circuit with flexible configuration, comprising: a light emitting device path; a current source for controlling the current amount on the light emitting device path, the current source receiving a relatively high reference voltage in a first state, and receiving a relatively low reference voltage in a second state; and a current source control circuit for controlling the current source, whereby when the light emitting device path is in normal use, the current source is set to the first state, and when the light emitting device path is not in normal use, the current source is set to the second state.

    摘要翻译: 本发明公开了一种具有柔性配置的背光控制电路,包括:发光器件路径; 用于控制发光器件路径上的电流量的电流源,电流源在第一状态下接收相对高的参考电压,并且在第二状态下接收相对低的参考电压; 以及用于控制电流源的电流源控制电路,由此当正常使用发光器件路径时,将电流源设置为第一状态,并且当发光器件路径不正常使用时,电流源 被设置为第二状态。

    Light emitting device array driver circuit and current splitter circuit and method of splitting current therefor
    80.
    发明授权
    Light emitting device array driver circuit and current splitter circuit and method of splitting current therefor 有权
    发光元件阵列驱动电路及分流电路及其分流电流的方法

    公开(公告)号:US08941325B2

    公开(公告)日:2015-01-27

    申请号:US13226091

    申请日:2011-09-06

    IPC分类号: H05B37/02 H05B33/08 G09G3/34

    摘要: The present invention discloses a current splitter circuit for splitting a supply current to multiple light emitting device strings of a light emitting device array. The current splitter circuit includes: a minimum selector circuit coupled to the multiple light emitting device strings to generate a minimum signal which indicates a minimum voltage of the light emitting device strings; and multiple current source circuits each including a first current source end coupled to a corresponding light emitting device string, a second current source end coupled to ground, and a current source control end receiving a current control signal related to the minimum signal, so as to control currents through the corresponding light emitting device string.

    摘要翻译: 本发明公开了一种用于将电源电流分离到发光器件阵列的多个发光器件串的电流分离器电路。 当前的分路器电路包括:耦合到多个发光器件串的最小选择器电路,以产生指示发光器件串的最小电压的最小信号; 以及多个电流源电路,每个电流源电路包括耦合到对应的发光器件串的第一电流源端,耦合到地的第二电流源端和接收与最小信号相关的电流控制信号的电流源控制端,以便 控制电流通过相应的发光器件串。