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    Optimizing grid-based compute graphs
    71.
    发明授权
    Optimizing grid-based compute graphs 有权

    公开(公告)号：US12217331B2

    公开(公告)日：2025-02-04

    申请号：US17955380

    申请日：2022-09-28

    Applicant: NVIDIA Corporation

    Inventor： Shekhar Dwivedi

    IPC: G06T11/00 ,  G06T1/20 ,  G06T1/60

    Abstract: Disclosed are apparatuses, systems, and techniques that enable compressed grid-based graph representations for efficient implementations of graph-mapped computing applications. The techniques include but are not limited to selecting a reference grid having a plurality of blocks, assigning nodes of the graph to blocks of the grid, and generating a graph representation that maps directions, relative to the reference grid, of nodal connections of the graph.

    REDUCING LEVEL OF DETAIL OF A POLYGON MESH TO DECREASE A COMPLEXITY OF RENDERED GEOMETRY WITHIN A SCENE
    73.
    发明申请
    REDUCING LEVEL OF DETAIL OF A POLYGON MESH TO DECREASE A COMPLEXITY OF RENDERED GEOMETRY WITHIN A SCENE 有权

    公开(公告)号：US20250037379A1

    公开(公告)日：2025-01-30

    申请号：US18915138

    申请日：2024-10-14

    Applicant: NVIDIA Corporation

    Inventor： Holger Heinrich Gruen

    IPC: G06T17/20 ,  G06T15/20

    Abstract: A method, computer readable medium, and system are disclosed for overlaying a cell onto a polygon meshlet. The polygon meshlet may include a grouping of multiple geometric shapes such as triangles, and the cell may include a square-shaped boundary. Additionally, every polygon (e.g., a triangle or other geometric shape) within the polygon meshlet that has at least one edge fully inside the cell is removed to create an intermediate meshlet. A selected vertex is determined from all vertices (e.g., line intersections) of the intermediate meshlet that are located within the cell, based on one or more criteria, and all the vertices of the intermediate meshlet that are located within the cell are replaced with the selected vertex to create a modified meshlet. The modified meshlet is then rendered (e.g., as part of a process to generate a scene to be viewed).

    MODIFYING OPERATIONS OF SYSTEMS BASED ON ERROR DETECTION
    75.
    发明申请
    MODIFYING OPERATIONS OF SYSTEMS BASED ON ERROR DETECTION 有权

    公开(公告)号：US20250036507A1

    公开(公告)日：2025-01-30

    申请号：US18359817

    申请日：2023-07-26

    Applicant: NVIDIA Corporation

    Inventor： Vito MAGNANIMO ,  Daniel PERRIN ,  Joy JACOBS ,  Hanne BUUR

    IPC: G06F11/07

    Abstract: Embodiments of the present disclosure relate to a method of detecting an error corresponding to a monitored system. The method may additionally include determining whether the error corresponds to a safety module associated with the monitored system that may have one or more operations that are deemed to affect safety or whether the error corresponds to a safety process associated with the monitored system that may have one or more operations that are deemed to affect safety. In some embodiments, the method may additionally include determining whether to continue operations of the monitored system, where the determination may be based at least on whether the error may correspond to a safety module associated with the monitored system or whether the error corresponds to a safety process associated with the monitored system.

    Latency determinations for human interface devices
    76.
    发明授权
    Latency determinations for human interface devices 有权

    公开(公告)号：US12212480B2

    公开(公告)日：2025-01-28

    申请号：US17064452

    申请日：2020-10-06

    Applicant: NVIDIA Corporation

    Inventor： David Lim ,  Hsien-Li Lin ,  Tom Jozef Denis Verbeure ,  Gerrit Slavenburg ,  Seth Schneider

    IPC: H04L43/08 ,  G06F3/14 ,  H04L43/065 ,  H04L43/0852 ,  H04L43/106

    Abstract: In various examples, latency of human interface devices (HIDs) may be accounted for in determining an end-to-end latency of a system. For example, when an input is received at an HID, an amount of time for the input to reach a connected device may be computed by the HID and included in a data packet transmitted by the HID device to the connected device. The addition of the peripheral latency to the end-to-end latency determination may provide a more comprehensive latency result for the system and, where the peripheral latency of an HID is determined to have a non-negligible contribution to the end-to-end latency, a new HID component may be implemented, a configuration setting associated with the HID component may be updated, and/or other actions may be taken to reduce the contribution of the peripheral latency to the overall latency of the system.

    FREQUENCY-VOLTAGE CONTROL FOR INPUT CURRENT LIMIT CIRCUIT
    80.
    发明申请
    FREQUENCY-VOLTAGE CONTROL FOR INPUT CURRENT LIMIT CIRCUIT 有权

    公开(公告)号：US20250028378A1

    公开(公告)日：2025-01-23

    申请号：US18222936

    申请日：2023-07-17

    Applicant: NVIDIA Corporation

    Inventor： Ziyi Xu ,  Zheng Wu ,  Ben Pei En Tsai ,  Xuan Wang

    IPC: G06F1/324 ,  H03L7/099

    Abstract: Technologies directed to input current limiter (ICL) circuits with frequency control loops are described. One integrated circuit includes a processing core and an ICL circuit. The ICL circuit can limit an input current to the processing core within a current limit of the processing core. The ICL circuit can determine an input current and a supply voltage provided to the processing core at a first time. The ICL circuit can reduce a clock of the processing core from a first clock frequency to a second clock frequency with a linear frequency drop based on the current limit, the input current, and the supply voltage. value, the second value, and the third value. The first clock frequency corresponds to a first voltage, and the second frequency corresponds to a second voltage. The ICL circuit can reduce the clock to a third clock frequency corresponding to a third voltage.

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