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公开(公告)号：US20140184278A1
公开(公告)日：2014-07-03
申请号：US14073494
申请日：2013-11-06
Applicant: STMICROELECTRONICS (SHENZHEN) R&D CO. LTD.
Inventor： Ni ZENG
IPC: H03K3/012
CPC classification number: H03K17/00 , H03K17/06 , H03K2017/066 , H03K2217/0036 , H03K2217/0063
Abstract: A driver circuit for driving a power transistor includes a converter having a first transistor and a second transistor coupled in series between a supply node and a reference node. The converter is configured to receive a first signal and in response thereto generate a second signal for selectively controlling status of the power transistor. The ratio of a first leakage current of the first transistor to a second leakage current of the second transistor is used in the generation of the second signal which is applied to the control terminal of a transistor switch that is selectively actuated to turn off the power transistor.
Abstract translation: 用于驱动功率晶体管的驱动电路包括具有串联耦合在供电节点和参考节点之间的第一晶体管和第二晶体管的转换器。 转换器被配置为接收第一信号，并响应于此产生用于选择性地控制功率晶体管状态的第二信号。 第一晶体管的第一泄漏电流与第二晶体管的第二漏电流之比用于产生施加到晶体管开关的控制端的第二信号，晶体管开关被选择性地致动以关断功率晶体管 。
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72.发明申请CURRENT SLOPE CONTROL METHOD AND APPARATUS FOR POWER DRIVER CIRCUIT APPLICATION 有权电流斜率控制方法和电源驱动电路应用的设备公开(公告)号：US20130300394A1
公开(公告)日：2013-11-14
申请号：US13875651
申请日：2013-05-02
Applicant: STMICROELECTRONICS (SHENZHEN) R&D CO. LTD.
Inventor： Meng Wang , Tao Tao Huang
IPC: H02M3/158
CPC classification number: G09G3/3225 , G09G3/20 , G09G3/3208 , G09G3/3648 , G09G2300/0842 , G09G2310/0259 , G09G2310/0291 , G09G2320/041 , G09G2320/043 , G09G2330/02 , G09G2330/025 , G09G2330/028 , H02M3/158 , H03K5/12 , H03K17/04123 , H03K17/687 , H03K2217/0063 , H03K2217/0072
Abstract: A low side driver includes a first transistor coupled in series with a second transistor at a low side voltage node for a load. A capacitance is configured to store a voltage and a voltage buffer circuit has an input coupled to receive the voltage stored by the capacitance and an output coupled to drive a control node of the second transistor with the stored voltage. A current source supplies current through a switch to the capacitance and the input of the voltage buffer circuit. The switch is configured to be actuated by an oscillating enable signal so as to cyclically source current from the current source to the capacitance and cause a stepped increase in the stored voltage which is applied by the buffer circuit to the control node of the second transistor.
Abstract translation: 低侧驱动器包括与用于负载的低侧电压节点与第二晶体管串联耦合的第一晶体管。 电容被配置为存储电压，并且电压缓冲器电路具有耦合以接收由电容存储的电压的输入和耦合以用所存储的电压驱动第二晶体管的控制节点的输出。 电流源通过开关将电流提供给电容和电压缓冲电路的输入。 该开关被配置为由振荡使能信号激励，以便将来自电流源的电流循环地引导到电容，并且使由缓冲电路施加到第二晶体管的控制节点的存储电压发生阶梯式增加。
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73.发明申请VOLTAGE CONTROLLED VARIABLE RESISTOR SUITABLE FOR LARGE SCALE SIGNAL APPLICATION 有权电压控制可变电阻适用于大规模信号应用公开(公告)号：US20130141152A1
公开(公告)日：2013-06-06
申请号：US13678782
申请日：2012-11-16
Applicant: STMICROELECTRONICS (SHENZHEN) R&D CO. LTD.
Inventor： Gang Zha
IPC: H03L5/00
CPC classification number: H03L5/00 , H03H11/245
Abstract: A voltage controlled variable resistor circuit is configured to variably attenuate a variable source signal. A fixed attenuation circuit is coupled to receive the variable source signal and output an attenuated variable source signal. The variable source signal is further applied across a variable resistive divider formed of a fixed resistive circuit and a variable resistive circuit. The variable resistive circuit has a first input configured to receive the attenuated variable source signal and a second input configured to receive a variable resistance control signal. The variable resistive circuit is configured to have a resistance which is variable in response to the attenuated variable source signal and the variable resistance control signal.
Abstract translation: 电压控制可变电阻电路被配置为可变地衰减可变源信号。 耦合固定衰减电路以接收可变源信号并输出衰减的可变源信号。 可变源信号进一步施加在由固定电阻电路和可变电阻电路构成的可变电阻分压器上。 可变电阻电路具有被配置为接收衰减的可变源信号的第一输入和被配置为接收可变电阻控制信号的第二输入。 可变电阻电路被配置为具有响应于衰减的可变源信号和可变电阻控制信号而变化的电阻。
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74.发明授权公开(公告)号：US12056912B2
公开(公告)日：2024-08-06
申请号：US17512080
申请日：2021-10-27
Inventor： Etienne Bossart , Ji Nan Li , Thomas Perotto
CPC classification number: G06V10/507 , G01S7/4816 , G01S17/08 , G06V20/00
Abstract: In an embodiment a method for detecting a presence of at least one object in a field of view of a time of flight sensor includes successively generating, by the time of flight sensor, histograms, each histogram comprising several classes associating a number of photons detected at a given acquisition period, adding several successively generated histograms so as to obtain a summed histogram and analyzing the summed histogram to detect the presence of at least one object in the field of view of the time of flight sensor.
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公开(公告)号：US11954260B2
公开(公告)日：2024-04-09
申请号：US17374815
申请日：2021-07-13
Inventor： Mirko Guarnera , Wenbin Yang , Enrico Rosario Alessi , Fabio Passaniti
CPC classification number: G06F3/017 , H04M1/0281
Abstract: A system and method for determining handedness in a device. The system including a first electrode, a second electrode, a sensor, and a processing circuit coupled to each other. The first electrode is placed at a first location, and the second electrode is placed at a second location on the device—the first location is different from the second location. The electrodes are configured to sense a variation in an electrostatic field in response to a user interacting with the device. The sensor detects a differential potential between the first electrode and the second electrode, and the processing circuit determines whether the user is interacting with the device using a left hand or a right hand. The determining is based on data received from the sensor corresponding to the differential potential.
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Patent Agency Ranking
公开(公告)号：US20240056046A1
公开(公告)日：2024-02-15
申请号：US18493282
申请日：2023-10-24
Applicant: STMicroelectronics (Shenzhen) R&D Co., Ltd.
Inventor： XiangSheng Li , Ru Feng Du
CPC classification number: H03G3/3005 , H03F3/187 , H04R3/00 , H04R29/00 , H03F2200/03 , H03G2201/103
Abstract: An audio amplifier includes: a buck controller configured to control an output voltage at a first supply terminal, the output voltage selected from a set including a plurality of output voltages, where the output voltage takes a settling time to settle; a first audio bridge including: a class-AB driver stage coupled to the first supply terminal, and a delay insertion circuit configured to receive a processed digital stream and provide the processed digital stream to the class-AB driver stage a delay time after receiving the processed digital stream, where the delay time is based on the settling time; and an audio amplitude detector configured to detect a first peak amplitude in the first digital audio stream, where the buck controller is configured to select a lowest output voltage from the set that is higher than the first peak amplitude plus a headroom voltage.
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公开(公告)号：US11831286B2
公开(公告)日：2023-11-28
申请号：US17241980
申请日：2021-04-27
Applicant: STMicroelectronics (Shenzhen) R & D Co. Ltd.
Inventor： XiangSheng Li , Ru Feng Du
CPC classification number: H03G3/3005 , H03F3/187 , H04R3/00 , H04R29/00 , H03F2200/03 , H03G2201/103
Abstract: An audio amplifier includes: a buck controller configured to control an output voltage at a first supply terminal, the output voltage selected from a set including a plurality of output voltages, where the output voltage takes a settling time to settle; a first audio bridge including: a class-AB driver stage coupled to the first supply terminal, and a delay insertion circuit configured to receive a processed digital stream and provide the processed digital stream to the class-AB driver stage a delay time after receiving the processed digital stream, where the delay time is based on the settling time; and an audio amplitude detector configured to detect a first peak amplitude in the first digital audio stream, where the buck controller is configured to select a lowest output voltage from the set that is higher than the first peak amplitude plus a headroom voltage.
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公开(公告)号：US11105836B2
公开(公告)日：2021-08-31
申请号：US16746444
申请日：2020-01-17
Inventor： Dino Costanzo , Cheng Pan Cai , Xi Yu Xu
IPC: G01R19/25 , H02P27/08 , H02M1/00 , G01R15/14 , H02M7/5387
Abstract: A three-phase load is powered by a PWM (e.g., SVPWM) driven DC-AC inverter having a single shunt-topology. A shunt voltage and a branch voltage of the inverter (across a transistor to be calibrated) are measured during a second period of each SVPWM sector, and the drain-to-source resistance of the calibrated transistor is calculated. During the fourth period of each SVPWM sector, the branch voltage is measured again, and another branch voltage across another transistor is measured. Using the drain-to-source resistance of the calibrated transistor and the voltage across the calibrated transistor measured during the fourth period, the phase current through the calibrated transistor is calculated. Using the other branch voltage measured during the fourth period and the drain-to-source resistance of its corresponding transistor (known from a prior SVPWM sector), the phase current through that transistor is calculated. From the two calculated phase currents, the other phase current can be calculated.
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公开(公告)号：US20210250010A1
公开(公告)日：2021-08-12
申请号：US17241980
申请日：2021-04-27
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.
Inventor： XiangSheng Li , Ru Feng Du
Abstract: An audio amplifier includes: a buck controller configured to control an output voltage at a first supply terminal, the output voltage selected from a set including a plurality of output voltages, where the output voltage takes a settling time to settle; a first audio bridge including: a class-AB driver stage coupled to the first supply terminal, and a delay insertion circuit configured to receive a processed digital stream and provide the processed digital stream to the class-AB driver stage a delay time after receiving the processed digital stream, where the delay time is based on the settling time; and an audio amplitude detector configured to detect a first peak amplitude in the first digital audio stream, where the buck controller is configured to select a lowest output voltage from the set that is higher than the first peak amplitude plus a headroom voltage.
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公开(公告)号：US20210232174A1
公开(公告)日：2021-07-29
申请号：US17159511
申请日：2021-01-27
Inventor： Ignazio PISELLO , Yu Yong WANG , Dario ARENA , Qi Yu LIU
IPC: G06F1/06 , G01R31/317
Abstract: A combinational circuit block has input pins configured to receive input digital signals and output pins configured to provide output digital signals as a function of the input digital signals received. A test input pin receives a test input signal. A test output pin provides a test output signal as a function of the test input signal received. A set of scan registers are selectively coupled to either the combinational circuit block or to one another so as to form a scan chain of scan registers serially coupled between the test input pin and the test output pin. The scan registers in the set of scan registers are clocked by a clock signal. At least one input register is coupled between the test input pin and a first scan register of the scan chain. The at least one input register is clocked by an inverted replica of the clock signal.
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