公开(公告)号：US20220164664A1

公开(公告)日：2022-05-26

申请号：US17510273

申请日：2021-10-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pierre Demaj ,  Laurent Folliot

IPC: G06N3/08 ,  G06F7/499 ,  G06F7/02

Abstract: According to one aspect, the disclosure proposes a method for updating an artificial neural network including initial weights stored in a memory at least in an integer format, which method includes: a processing unit determining the error gradients at the output of the layers of the neural network, the processing unit retrieving the initial weights from memory, the processing unit updating the initial weights comprising, for each initial weight, a first calculation of a corrected weight, in the integer format of this initial weight, the processing unit replacing the value of the initial weights stored in the memory by the value of the corrected weights.

公开(公告)号：US11336268B2

公开(公告)日：2022-05-17

申请号：US17128890

申请日：2020-12-21

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Bruno Gailhard

IPC: H03K3/03 ,  H03K5/01

Abstract: Integrated circuit, comprising at least one ring oscillator including a succession of inverters looped back to form the ring, the at least one oscillator being intended to operate at a desired output frequency and configured so that the inverter transistors operate in or near their temperature inversion zone.

公开(公告)号：US20220150680A1

公开(公告)日：2022-05-12

申请号：US17649146

申请日：2022-01-27

Applicant: STMicroelectronics (Rousset) SAS ,  STMICROELECTRONICS GMBH

Inventor： Thierry Meziache ,  Pierre Rizzo ,  Alexandre Charles ,  Juergen Boehler

IPC: H04W4/80 ,  G06K7/00 ,  G06K7/10 ,  H04B5/00

Abstract: A device, including a main element and a set of at least two auxiliary elements, said main element including a master SWP interface, each auxiliary element including a slave SWP interface connected to said master SWP interface of said NFC element through a controllably switchable SWP link and management means configured to control said SWP link switching for selectively activating at once only one slave SWP interface on said SWP link.

公开(公告)号：US20220149894A1

公开(公告)日：2022-05-12

申请号：US17499371

申请日：2021-10-12

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Tramoni

IPC: H04B5/00 ,  H02J50/12

Abstract: An embodiment of the present description concerns a method wherein a time of beginning of a periodic step of activation of a near-field communication circuit of a first device, charged in near field by a second device, is adjusted according to a frequency of an electromagnetic field emitted by the second device.

公开(公告)号：US11322503B2

公开(公告)日：2022-05-03

申请号：US17141498

申请日：2021-01-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Fabrice Marinet

IPC: G11C17/16 ,  H01L27/112 ,  H01L23/58 ,  H01L23/528 ,  G11C17/18 ,  H01L23/525 ,  H01L23/522

Abstract: An integrated circuit includes a memory cell incorporating an antifuse device. The antifuse device includes a state transistor having a control gate and a second gate that is configured to be floating. A dielectric layer between the control gate and the second gate is selectively blown in order to confer a broken-down state on the antifuse device where the second gate is electrically coupled to the control gate for storing a first logic state. Otherwise, the antifuse device is in a non-broken-down state for storing a second logic state.

公开(公告)号：US20220130904A1

公开(公告)日：2022-04-28

申请号：US17507624

申请日：2021-10-21

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe BOIVIN

IPC: H01L27/24 ,  H01L45/00

Abstract: The present description concerns a method of forming a track in a first layer, including a) forming a cavity in the first layer; b) totally filling the cavity with a first material; and c) partially removing the first material from the upper portion of the cavity, to form the track made of the first material.

公开(公告)号：US20220129568A1

公开(公告)日：2022-04-28

申请号：US17484246

申请日：2021-09-24

Applicant: STMicroelectronics (Rousset) SAS ,  Proton World International N.V.

Inventor： Olivier Van Nieuwenhuyze ,  Alexandre Charles

IPC: G06F21/60

Abstract: The present description discloses a secure element and a communication method, configured to implement at least one first application, and including a circuit configured to record routing data and a list and parameters of communication protocols compatible with the first application, verify the compatibility of a first communication protocol used by first messages intended for the first application with the protocols of the list, convert the first messages into second messages by using a second communication protocol in response to the first protocol not being compatible with at least one of the protocols of the list, and direct the second messages to the first application by using the routing data of the first application.

公开(公告)号：US20220120589A1

公开(公告)日：2022-04-21

申请号：US17504021

申请日：2021-10-18

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA

IPC: G01D5/24 ,  H01L27/06 ,  H01L29/786 ,  H01L49/02 ,  H01L29/66 ,  H01L21/28

Abstract: An integrated circuit includes a first substrate. A MOS transistor has a first polysilicon region electrically isolated from the first substrate and including a gate region. A second polysilicon region is electrically isolated from the first polysilicon region and from the first substrate. The second polysilicon region includes a source region, a substrate region and a drain region of the MOS transistor. The first polysilicon region is located between an area of the first substrate and the second polysilicon region.

公开(公告)号：US11303118B2

公开(公告)日：2022-04-12

申请号：US17165557

申请日：2021-02-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: H02H9/04

Abstract: The present disclosure relates to a device including a rectifying bridge including: a branch connected between first and second nodes; another branch including first and second MOS transistors series-connected between the first and second nodes and having their sources coupled together; a resistor connecting the gate of the first transistor to the second node; another resistor connecting the gate of the second transistor and the first node; and for each transistor, a circuit including first and second terminals respectively connected to the drain and to the gate of the transistor, and being configured to electrically couple its first and second terminals when a voltage between the first terminal of the circuit and the first terminal of the other circuit is greater than a threshold of the circuit.

公开(公告)号：US11296626B2

公开(公告)日：2022-04-05

申请号：US16921557

申请日：2020-07-06

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Gwenael Maillet ,  Jean-Louis Labyre ,  Gilles Bas

IPC: H02M1/44 ,  H02P7/29 ,  G05B19/042 ,  G06K19/07 ,  G06K19/00 ,  H02P7/03

Abstract: Control over the operation of an electrically-controlled motor is supported by an interface circuit between the electrically-controlled motor and a near-field radio frequency communication controller. The interface circuit includes a first circuit that receives at least one control set point through a near-field radio frequency communication issued by the near-field radio frequency communication controller. A second circuit of the interface generates one or more electric signals in pulse width modulation based on the control set point.