公开(公告)号：US11921834B2

公开(公告)日：2024-03-05

申请号：US16249804

申请日：2019-01-16

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Fabrice Marinet

IPC: G06F21/00 ,  B41J2/175 ,  G06F21/44 ,  G06K15/02 ,  G06F21/73

CPC classification number: G06F21/44 ,  B41J2/17546 ,  B41J2/17566 ,  G06K15/1822 ,  G06F21/73 ,  G06F2221/2129

Abstract: A method of authenticating a first electronic circuit includes generating a first signature using the first electronic circuit, the generating of the first signature being based on states of a plurality of electric nodes distributed within the first electronic circuit. A second signature is generated using a second electronic circuit, the generating of the second signature being based on states of a plurality of electric nodes distributed within the second electronic circuit. The first signature is compared to the second signature. The first electronic circuit is authenticated based on the comparison of the first signature to the second signature.

公开(公告)号：US11621051B2

公开(公告)日：2023-04-04

申请号：US17647793

申请日：2022-01-12

Applicant: STMicroelectronics (Rousset) SAS ,  STMICROELECTRONICS SA

Inventor： Stephane Denorme ,  Philippe Candelier ,  Joel Damiens ,  Fabrice Marinet

IPC: G11C11/34 ,  G11C29/52 ,  G11C17/12

Abstract: A device includes a first switch, a first irreversibly programmable memory point, and a second irreversibly programmable memory point coupled in parallel with the first irreversibly programmable memory point. The first switch and the parallel combination of the first and second irreversibly programmable memory points are coupled in series between a first node and a second node.

公开(公告)号：US11367720B2

公开(公告)日：2022-06-21

申请号：US16518436

申请日：2019-07-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Fabrice Marinet

IPC: H01L27/02 ,  H01L23/525

Abstract: An integrated circuit includes a circuit module storing sensitive data. An electrically conductive body at a floating potential is located in the integrated circuit and holds an initial amount of electric charge. In response to an attack attempting to access the sensitive data, electric charge is collected on the electrically conductive body. A protection circuit is configured to ground an output of the circuit module, and thus preclude access to the sensitive data, in response to collected amount of electric charge on the electrically conductive body differing from the initial amount and exceeding a threshold.

公开(公告)号：US11322503B2

公开(公告)日：2022-05-03

申请号：US17141498

申请日：2021-01-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Fabrice Marinet

IPC: G11C17/16 ,  H01L27/112 ,  H01L23/58 ,  H01L23/528 ,  G11C17/18 ,  H01L23/525 ,  H01L23/522

Abstract: An integrated circuit includes a memory cell incorporating an antifuse device. The antifuse device includes a state transistor having a control gate and a second gate that is configured to be floating. A dielectric layer between the control gate and the second gate is selectively blown in order to confer a broken-down state on the antifuse device where the second gate is electrically coupled to the control gate for storing a first logic state. Otherwise, the antifuse device is in a non-broken-down state for storing a second logic state.

公开(公告)号：US10923484B2

公开(公告)日：2021-02-16

申请号：US16546002

申请日：2019-08-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Fabrice Marinet

IPC: G11C17/16 ,  H01L27/112 ,  H01L23/58 ,  H01L23/528 ,  G11C17/18 ,  H01L23/525 ,  H01L23/522

Abstract: An integrated circuit includes a memory cell incorporating an antifuse device. The antifuse device includes a state transistor having a control gate and a second gate that is configured to be floating. A dielectric layer between the control gate and the second gate is selectively blown in order to confer a broken-down state on the antifuse device where the second gate is electrically coupled to the control gate for storing a first logic state. Otherwise, the antifuse device is in a non-broken-down state for storing a second logic state.

公开(公告)号：US20200035671A1

公开(公告)日：2020-01-30

申请号：US16518436

申请日：2019-07-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Fabrice Marinet

IPC: H01L27/02 ,  H01L23/525

Abstract: An integrated circuit includes a circuit module storing sensitive data. An electrically conductive body at a floating potential is located in the integrated circuit and holds an initial amount of electric charge. In response to an attack attempting to access the sensitive data, electric charge is collected on the electrically conductive body. A protection circuit is configured to ground an output of the circuit module, and thus preclude access to the sensitive data, in response to collected amount of electric charge on the electrically conductive body differing from the initial amount and exceeding a threshold.

公开(公告)号：US20180131508A1

公开(公告)日：2018-05-10

申请号：US15862962

申请日：2018-01-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Fabrice Marinet ,  Mathieu Lisart

IPC: H04L9/08 ,  G06F12/14 ,  G06F21/78 ,  G06F21/77 ,  G06F21/62 ,  G06F3/06 ,  G06F11/14

CPC classification number: H04L9/088 ,  G06F3/0623 ,  G06F3/0644 ,  G06F3/0688 ,  G06F11/1458 ,  G06F12/1408 ,  G06F21/62 ,  G06F21/77 ,  G06F21/78 ,  G06F2212/402

Abstract: A method for processing content stored on a component is disclosed. A first partition of a first memory is encrypted with a first encryption key and a second partition of the first memory is encrypted with a second encryption key. The second encryption key is different from the first encryption key. The first encryption key is stored in a storage register of the component and the second encryption key is stored in a first location of a non-volatile memory. A memory address of the first location is stored in the first partition of the first memory.

公开(公告)号：US09900151B2

公开(公告)日：2018-02-20

申请号：US15056844

申请日：2016-02-29

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Fabrice Marinet ,  Mathieu Lisart

IPC: G06F11/30 ,  G06F12/14 ,  H04L9/08 ,  G06F21/78 ,  G06F11/14 ,  G06F21/62 ,  G06F21/77 ,  G06F3/06

CPC classification number: H04L9/088 ,  G06F3/0623 ,  G06F3/0644 ,  G06F3/0688 ,  G06F11/1458 ,  G06F12/1408 ,  G06F21/62 ,  G06F21/77 ,  G06F21/78 ,  G06F2212/402

Abstract: A method for processing content stored on a component is disclosed. A first partition of a first memory is encrypted with a first encryption key and a second partition of the first memory is encrypted with a second encryption key. The second encryption key is different from the first encryption key. The first encryption key is stored in a storage register of the component and the second encryption key is stored in a first location of a non-volatile memory. A memory address of the first location is stored in the first partition of the first memory.

公开(公告)号：US20170344310A1

公开(公告)日：2017-11-30

申请号：US15331470

申请日：2016-10-21

Applicant: STMICROELECTRONICS (ROUSSET) SAS ,  PROTON WORLD INTERNATIONAL N.V.

Inventor： Michael Peeters ,  Fabrice Marinet ,  Jean-Louis Modave ,  Fabrice Romain

IPC: G06F3/06 ,  G06F21/56

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/064 ,  G06F3/0673 ,  G06F21/52 ,  G06F21/554 ,  G06F21/566 ,  G06F2221/034 ,  G09C1/00 ,  H04L9/004 ,  H04L2209/046 ,  H04L2209/12

Abstract: An algorithm execution method includes carrying out a first execution of the algorithm by a processing unit, sending at least one first result, which is to be written into a memory, to a memory management circuit, and storing said first result into a first area of the volatile memory. The method also includes carrying out a second execution of the algorithm by the processing unit, sending at least one second result, which is to be written into the memory, to the memory management circuit, and applying, by means of the memory management circuit, a different processing for the at least one second result in the second execution than was applied for the at least one first results in the first execution.

公开(公告)号：US11715705B2

公开(公告)日：2023-08-01

申请号：US16932082

申请日：2020-07-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Fabrice Marinet

IPC: H01L29/788 ,  G06F21/75 ,  G06F21/79 ,  H01L23/522 ,  H10B41/35 ,  H01L23/00 ,  G06F21/87

CPC classification number: H01L23/573 ,  G06F21/75 ,  G06F21/79 ,  H01L23/5223 ,  H01L23/576 ,  H01L29/7883 ,  H10B41/35 ,  G06F21/87

Abstract: An integrated circuit memory includes a state transistor having a floating gate which stores a respective data value. A device for protecting the data stored in the memory includes a capacitive structure having a first electrically-conducting body coupled to the floating gate of the state transistor, a dielectric body, and a second electrically-conducting body coupled to a ground terminal. The dielectric body is configured, if an aqueous solution is brought into contact with the dielectric body, to electrically couple the floating gate and the ground terminal so as to modify the charge on the floating gate and to lose the corresponding data. Otherwise, the dielectric body is configured to electrically isolate the floating gate and the ground terminal.