公开(公告)号：US20210172791A1

公开(公告)日：2021-06-10

申请号：US17116851

申请日：2020-12-09

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Olivier LE NEEL ,  Stephane MONFRAY

IPC: G01J1/04 ,  H01L27/144 ,  G02B5/20 ,  G01J1/44

Abstract: A light sensor includes a first pixel and a second pixel. Each pixel has a photoconversion area. A band-stop Fano resonance filter is arranged over the first pixel. The second pixel includes no Fano resonance filter. Signals output from the first and second pixels are processed to determine information representative of the quantity of light received by the light sensor during an illumination phase in a rejection band of the band-stop Fano resonance filter.

公开(公告)号：US11031433B2

公开(公告)日：2021-06-08

申请号：US16270989

申请日：2019-02-08

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Frederic Lalanne ,  Laurent Gay ,  Pascal Fonteneau ,  Yann Henrion ,  Francois Guyader

IPC: H01L27/146 ,  H01L21/02 ,  H01L21/306

Abstract: Image sensors and methods of manufacturing image sensors are provided herein. In an embodiment, a method of manufacturing an image sensor includes forming a structure having a front side and a back side. The structure includes a semiconductor layer extending between the front side and the back side of the structure, and a capacitive insulation wall extending through the semiconductor layer between the front side and the back side of the structure. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductive or semiconductor material. The method further includes selectively etching, from the back side of the structure, portions of the semiconductor layer and the region of conductive or semiconductor material, while retaining adjacent portions of the first and second insulating walls.

公开(公告)号：US20210151600A1

公开(公告)日：2021-05-20

申请号：US17095003

申请日：2020-11-11

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean JIMENEZ MARTINEZ

IPC: H01L29/78 ,  H01L27/06 ,  H01L29/66 ,  H01L29/73

Abstract: An integrated circuit includes an N-type laterally diffused metal-oxide semiconductor (NLDMOS) transistor including an active semiconductor substrate region having P-type conductivity. The integrated circuit further includes a buried semiconductor region having N+-type conductivity underneath the active substrate region. The buried semiconductor region is more heavily doped than the active semiconductor substrate region.

公开(公告)号：US10998431B2

公开(公告)日：2021-05-04

申请号：US16571532

申请日：2019-09-16

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pascal Chevalier ,  Alexis Gauthier

IPC: H01L29/737 ,  H01L29/66 ,  H01L29/08 ,  H01L29/732 ,  H01L29/10 ,  H01L29/06 ,  H01L29/165

Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector connection region. A first epitaxial region forms a collector region doped with a first conductivity type on the collector connection region. The collector region includes a counter-doped region of a second conductivity type. A second epitaxial region forms a base region of a second conductivity type on the first epitaxial region. Deposited semiconductor material forms an emitter region of the first conductivity type on the second epitaxial region. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.

公开(公告)号：US10914896B2

公开(公告)日：2021-02-09

申请号：US16199845

申请日：2018-11-26

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Nicolas Michit ,  Patrick Le Maitre

IPC: G02B6/12 ,  G02B6/26 ,  G02B6/42 ,  G02B6/34 ,  G02B6/293 ,  H04Q11/00 ,  G02B6/35

Abstract: An elementary photonic interconnect switch is integrated into an optoelectronic chip and includes four simple photonic interconnect switches. Each simple photonic interconnect switch has two optical waveguides that cross and are linked by a ring resonator having one ring. A basic photonic interconnect switch, a complex photonic interconnect switch and/or a photonic interconnect network are integrated into an optoelectronic chip and including at least two elementary photonic interconnect switches.

公开(公告)号：US20210018815A1

公开(公告)日：2021-01-21

申请号：US16931090

申请日：2020-07-16

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Frédéric Boeuf ,  Cyrille Barrera

IPC: G02F1/225 ,  G02F1/025 ,  G02F1/035

Abstract: A capacitive electro-optical modulator includes a silicon layer, a germanium or silicon-germanium strip overlying the silicon layer, and a silicon strip overlying the germanium or silicon-germanium strip. The silicon strip is wider than the germanium or silicon-germanium strip. An insulator is laterally adjacent the germanium or silicon-germanium strip and the silicon strip and has an upper surface that is flush with an upper surface of the silicon strip. An insulating layer overlies the insulator and the silicon strip. A layer of III-V material overlies the insulating layer. The layer of III-V material is formed as a third strip arranged facing the silicon strip and separated therefrom by a portion of the insulating layer.

公开(公告)号：US10795189B2

公开(公告)日：2020-10-06

申请号：US16247096

申请日：2019-01-14

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Stephane Monfray

IPC: G02F1/35 ,  G02F1/025

Abstract: An electro-optical phase modulator includes a waveguide made from a stack of strips. The stack includes a first strip made of a doped semiconductor material of a first conductivity type, a second strip made of a conductive material or of a doped semiconductor material of a second conductivity type, and a third strip made of a doped semiconductor material of the first conductivity type. The second strip is separated from the first strip by a first interface layer made of a dielectric material, and the third strip is separated from the second strip by a second interface layer made of a dielectric material.

公开(公告)号：US20200313023A1

公开(公告)日：2020-10-01

申请号：US16825298

申请日：2020-03-20

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Arnaud TOURNIER ,  Boris RODRIGUES GONCALVES ,  Francois ROY

IPC: H01L31/107 ,  H01L27/146

Abstract: An electronic device is provided that includes a photodiode. The photodiode includes a semiconductor region coupled to a node of application of a first voltage, and at least one semiconductor wall. The at least one semiconductor wall extends along at least a height of the photodiode and partially surrounds the semiconductor region.

公开(公告)号：US20200274722A1

公开(公告)日：2020-08-27

申请号：US16783631

申请日：2020-02-06

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Marc Mantelli ,  Stephan Niel ,  Arnaud Regnier

IPC: H04L9/32 ,  G06F21/72 ,  G06F21/60 ,  G11C16/04 ,  G11C16/28 ,  G11C16/10 ,  G11C16/30

Abstract: In accordance with an embodiment, a physically unclonable function device includes a set of transistor pairs, transistors of the set of transistor pairs having a randomly distributed effective threshold voltage belonging to a common random distribution; a differential read circuit configured to measure a threshold difference between the effective threshold voltages of transistors of transistor pairs of the set of transistor pairs, and to identify a transistor pair in which the measured threshold difference is smaller than a margin value as being an unreliable transistor pair; and a write circuit configured to shift the effective threshold voltage of a transistor of the unreliable transistor pair to be inside the common random distribution.

公开(公告)号：US20200266310A1

公开(公告)日：2020-08-20

申请号：US16789997

申请日：2020-02-13

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Boris RODRIGUES GONCALVES ,  Arnaud TOURNIER

IPC: H01L31/0352

Abstract: A photodiode include a first substrate layer of a first dopant type and a second substrate layer of a second dopant type on top of the first substrate layer. Semiconductor walls are provided in a semiconductor substrate which includes the first and second substrate layers. The semiconductor walls include: two outer semiconductor walls and at least one inside semiconductor wall positioned between the two outer semiconductor walls. Each inside semiconductor wall is located between two semiconductor walls having longer length.