公开(公告)号：US11216373B2

公开(公告)日：2022-01-04

申请号：US16887713

申请日：2020-05-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Shaizeen Aga ,  Nuwan Jayasena ,  Johnathan Alsop

IPC: G06F12/06 ,  G11C11/408

Abstract: A memory controller may be configured with command logic that is capable of sending a memory access command having incomplete address information via a command/address bus that connects the memory controller to memory modules. The memory controller may send the memory access command via the bus for accessing data stored at memory locations of the memory modules. The memory locations may correspond to different near-memory generated reflecting that the data is not address aligned across the memory modules. Nonetheless, because of the near-memory address generation, the memory controller can send the memory access command having incomplete address information for accessing the data stored at the different addresses, as opposed to having to send multiple memory access commands specifying complete address information on the bus for accessing the data at the different addresses, thereby conserving usage of the available bus bandwidth, reducing power consumption, and increasing compute throughput.

公开(公告)号：US20210374055A1

公开(公告)日：2021-12-02

申请号：US16887713

申请日：2020-05-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Shaizeen Aga ,  Nuwan Jayasena ,  Johnathan Alsop

IPC: G06F12/06 ,  G11C11/408

Abstract: A memory controller may be configured with command logic that is capable of sending a memory access command having incomplete address information via a command/address bus that connects the memory controller to memory modules. The memory controller may send the memory access command via the bus for accessing data stored at memory locations of the memory modules. The memory locations may correspond to different near-memory generated reflecting that the data is not address aligned across the memory modules. Nonetheless, because of the near-memory address generation, the memory controller can send the memory access command having incomplete address information for accessing the data stored at the different addresses, as opposed to having to send multiple memory access commands specifying complete address information on the bus for accessing the data at the different addresses, thereby conserving usage of the available bus bandwidth, reducing power consumption, and increasing compute throughput.

公开(公告)号：US20210209192A1

公开(公告)日：2021-07-08

申请号：US17208526

申请日：2021-03-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Shaizeen Aga ,  Nuwan Jayasena ,  Allen H. Rush ,  Michael Ignatowski

IPC: G06F17/16 ,  G06F7/53 ,  G06F15/80

Abstract: A processing device is provided which comprises memory configured to store data and a plurality of processor cores in communication with each other via first and second hierarchical communication links. Processor cores of a first hierarchical processor core group are in communication with each other via the first hierarchical communication links and are configured to store, in the memory, a sub-portion of data of a first matrix and a sub-portion of data of a second matrix. The processor cores are also configured to determine a product of the sub-portion of data of the first matrix and the sub-portion of data of the second matrix, receive, from another processor core, another sub-portion of data of the second matrix and determine a product of the sub-portion of data of the first matrix and the other sub-portion of data of the second matrix.

公开(公告)号：US11055150B2

公开(公告)日：2021-07-06

申请号：US15952143

申请日：2018-04-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan Jayasena ,  Amin Farmahini-Farahani ,  David A. Roberts

IPC: G06F9/52 ,  G06F9/48 ,  G06F9/50

Abstract: A thread holding a lock notifies a sleeping thread that is waiting on the lock that the lock holding thread is “about” to release the lock. In response to the notification, the waiting thread is woken up. While the waiting thread is woken up, the lock holding thread completes other operations prior to actually releasing the lock and then releases the lock. The notification to the waiting thread hides latency associated with waking up the waiting thread by allowing operations that wake up the waiting thread to occur while the lock holding thread is performing the other operations prior to releasing the thread.

公开(公告)号：US10782918B2

公开(公告)日：2020-09-22

申请号：US16123837

申请日：2018-09-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Shaizeen Aga ,  Nuwan Jayasena

IPC: G06F3/06 ,  G06F11/10

Abstract: Methods, systems, and devices for near-memory data-dependent gathering and packing of data stored in a memory. A processing device extracts a function, a memory source address, and a memory destination address from a near-memory data-dependent gathering and packing primitive. A signal to perform gathering and packing operations based on the primitive is sent to near-memory processing circuitry of a memory device. The near-memory processing circuitry receives the signal, gathers data from the memory device based on the function and the memory source address, and packs the gathered data into the memory device based on the memory destination address.

公开(公告)号：US10749545B1

公开(公告)日：2020-08-18

申请号：US16557602

申请日：2019-08-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander D. Breslow ,  Nuwan Jayasena ,  John Kalamatianos

IPC: H03M7/40 ,  H03M7/30 ,  G06F16/901 ,  G06F16/903

Abstract: A data storage system performs partial compression and decompression of a set of memory items. The memory items each include a data block and a tag with a prefix making up at least part of the tag. The memory items are ordered based on the prefixes. A code word is created containing compressed information representing values of the prefixes for the set of memory items. The code word and block data for each of the memory items are stored in a memory. The code word is decompressed to recover the prefixes.

公开(公告)号：US20200057717A1

公开(公告)日：2020-02-20

申请号：US16104567

申请日：2018-08-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan Jayasena ,  Amin Farmahini Farahani ,  Michael Ignatowski

IPC: G06F12/0804 ,  G06F12/0862 ,  G06F13/16

Abstract: In one form, a data processing system includes a host integrated circuit having a memory controller, a memory bus coupled to the memory controller, and a memory module. The memory module includes a bulk memory and a memory module scratchpad coupled to the bulk memory, wherein the memory module scratchpad has a lower access overhead than the bulk memory. The memory controller selectively provides predetermined commands over the memory bus to cause the memory module to copy data between the bulk memory and the memory module scratchpad without conducting data on the memory bus in response to a data movement decision.

公开(公告)号：US10382410B2

公开(公告)日：2019-08-13

申请号：US14993455

申请日：2016-01-12

Applicant: Advanced Micro Devices Inc.

Inventor： Nuwan Jayasena ,  Dong Ping Zhang

IPC: H04L29/06 ,  G06F12/14 ,  H04L9/32

Abstract: A processing system includes a processing module having a first interface coupleable to an interconnect. The first interface includes a first cryptologic engine to encrypt a representation of store data of a store operation and a memory address using a first key and a first feedback-based cryptologic process to generate first encrypted data and an encrypted memory address. A memory module includes a second interface coupled to the interconnect. The second interface includes a second cryptologic engine to decrypt the first encrypted data and the encrypted memory address using a second key and a second feedback-based cryptologic process to generate a copy of the representation of the store data and a copy of the memory address. The second interface further is to store the copy of the representation of the store data to a memory location of the memory core based on the copy of the memory address.

公开(公告)号：US10310981B2

公开(公告)日：2019-06-04

申请号：US15268953

申请日：2016-09-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Yasuko Eckert ,  Nuwan Jayasena ,  Reena Panda ,  Onur Kayiran ,  Michael W. Boyer

IPC: G06F12/00 ,  G06F12/0862 ,  G06F13/00 ,  G06F13/28

Abstract: A method and apparatus for performing memory prefetching includes determining whether to initiate prefetching. Upon a determination to initiate prefetching, a first memory row is determined as a suitable prefetch candidate, and it is determined whether a particular set of one or more cachelines of the first memory row is to be prefetched.

公开(公告)号：US10268416B2

公开(公告)日：2019-04-23

申请号：US14924881

申请日：2015-10-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan Jayasena ,  David A. Roberts

IPC: G06F3/06 ,  G06F12/08 ,  G06F12/0817

Abstract: A memory-to-memory copy operation control system includes a processor configured to receive an instruction to perform a memory-to-memory copy operation and a memory module network in communication with the processor. The memory module network has a plurality of memory modules that include a proximal memory module in direct communication with the processor and one or more additional memory modules in communication with the processor via the proximal memory module. The system also includes a memory controller in communication with the processor and the network of memory modules. The processor is configured to issue a first command causing data to be copied from a first memory module to a second memory module without sending the data to the processor or the memory controller.