公开(公告)号：US06380085B2

公开(公告)日：2002-04-30

申请号：US09750061

申请日：2000-12-29

申请人： Akio Nishida ,  Kikuo Kusukawa ,  Toshiaki Yamanaka ,  Natsuki Yokoyama ,  Shinichiro Kimura ,  Norio Suzuki ,  Osamu Tsuchiya ,  Atsushi Ogishima

发明人： Akio Nishida ,  Kikuo Kusukawa ,  Toshiaki Yamanaka ,  Natsuki Yokoyama ,  Shinichiro Kimura ,  Norio Suzuki ,  Osamu Tsuchiya ,  Atsushi Ogishima

IPC分类号： H01L21302

CPC分类号： H01L27/10894 ,  H01L21/31053 ,  H01L21/76229 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/10814

摘要： In a method of manufacturing a semiconductor device having a memory mat portion in which an active region and a field region are formed densely, after a polishing stopper film is deposited on a semiconductor substrate, there are formed grooves by etching a polishing stopper film of a field region and the semiconductor substrate. Then, after an insulating film is deposited so as to fill the grooves, then insulating film is partly removed from the memory mat portion by etching. Under this state, the insulating film is chemically mechanically polished until the polishing stopper film is exposed. The film thickness of the polishing stopper film on the active region can be reduced, and an electrical element isolation characteristic of the field region can be improved. At the same time, upon chemical mechanical polishing, a silicon substrate can be prevented from being exposed at the central portion of the memory mat portion and the insulating film can be prevented from being left on the silicon nitride film near the outer periphery, thereby making it possible to form elements having uniform electrical characteristics on all active regions of the memory mat portion.

摘要翻译： 在制造半导体器件的方法中，其具有密集形成有源区和场区的存储垫部分，在半导体衬底上沉积抛光阻挡膜之后，通过蚀刻抛光阻挡膜形成凹槽 场区域和半导体衬底。 然后，在沉积绝缘膜以填充凹槽之后，通过蚀刻部分地从存储垫部分去除绝缘膜。 在这种状态下，绝缘膜被化学机械抛光直到抛光阻挡膜露出。 能够减少有源区域上的研磨停止膜的膜厚，能够提高场区域的电气元件隔离特性。 同时，在化学机械抛光时，可以防止硅衬底暴露在存储垫部分的中心部分，并且可以防止绝缘膜留在靠近外周的氮化硅膜上，从而使 可以在存储垫部分的所有有效区域上形成具有均匀电特性的元件。

公开(公告)号：US06285566B1

公开(公告)日：2001-09-04

申请号：US09234958

申请日：1999-01-21

申请人： Koji Nakahira ,  Ryuji Okamura ,  Ryota Tani ,  Akio Nishida

发明人： Koji Nakahira ,  Ryuji Okamura ,  Ryota Tani ,  Akio Nishida

IPC分类号： H02M3335

CPC分类号： H02M3/3385

摘要： A self-oscillation switching power supply apparatus of the ringing choke converter type comprises a transformer T including a primary winding N1, a secondary winding N2, and a feedback winding NB; a switching transistor Q1 which oscillates in a self-oscillating fashion in response to a feedback signal from the feedback winding NB thereby turning on and off the current flowing through the primary winding; a rectifying and smoothing circuit connected to the secondary winding; an oscillation frequency control circuit including a control transistor Q3 for controlling a control signal input to the switching transistor Q1 thereby controlling the control transistor Q3 so as to extend the off-time in the self-oscillation period of the switching transistor Q1; and an oscillation frequency control disabling circuit for disabling the control of the control transistor Q3 in accordance with a remote signal.

摘要翻译： 一种振铃式转换器的自振荡开关电源装置包括一个变压器T，它包括初级绕组N1，次级绕组N2和反馈绕组NB; 响应于来自反馈绕组NB的反馈信号以自振荡方式振荡的开关晶体管Q1，从而导通和关闭流过初级绕组的电流; 连接到次级绕组的整流和平滑电路; 振荡频率控制电路，包括用于控制输入到开关晶体管Q1的控制信号的控制晶体管Q3，从而控制控制晶体管Q3，以便在开关晶体管Q1的自激振荡周期中延长关断时间; 以及用于根据远程信号禁止控制晶体管Q3的控制的振荡频率控制禁止电路。

公开(公告)号：US06185112B2

公开(公告)日：2001-02-06

申请号：US09232786

申请日：1999-01-19

申请人： Akio Nishida ,  Koji Nakahira ,  Ryota Tani

发明人： Akio Nishida ,  Koji Nakahira ,  Ryota Tani

IPC分类号： H02M3335

CPC分类号： H02M3/3385 ,  H02M2001/0032 ,  Y02B70/16

摘要： A switching power supply device comprises: a transformer having a primary winding, a secondary winding and a feedback winding; a switching element connected in series with the primary winding; a controlling element connected to a control terminal of the switching element; a controlling circuit provided between the controlling element and the feedback winding; a rectifying circuit connected to the secondary winding; and a frequency limiting circuit including a charging circuit and a kick voltage absorbing circuit. The charging circuit is adapted to be charged by a voltage reverse in polarity, produced in the feedback winding. The kick voltage absorbing circuit absorbs a current developed by a kick voltage in the feedback winding, by discharge of the charging circuit, whereby the frequency limiting circuit reducing the switching frequency of the switching element by prolongation of the off-state time-period of the switching element in correspondence to a light load signal from a load when the load is light.

摘要翻译： 开关电源装置包括：具有初级绕组，次级绕组和反馈绕组的变压器; 与初级绕组串联连接的开关元件; 连接到所述开关元件的控制端子的控制元件; 控制电路，设置在控制元件和反馈绕组之间; 连接到次级绕组的整流电路; 以及包括充电电路和脚踏电压吸收电路的限频电路。 充电电路适于由反馈绕组中产生的极性反向电压充电。 脚踏电压吸收电路通过充电电路的放电吸收由反馈绕组中的脚踏电压产生的电流，由此频率限制电路通过延长开关元件的截止状态时间段来降低开关元件的开关频率 开关元件对应于来自负载的轻负载信号。

公开(公告)号：US6160720A

公开(公告)日：2000-12-12

申请号：US477543

申请日：2000-01-04

申请人： Akio Nishida ,  Koji Nakahira

发明人： Akio Nishida ,  Koji Nakahira

IPC分类号： H02J1/00 ,  H02J9/00 ,  H02M3/28 ,  H02M3/335 ,  H02M3/338 ,  H02M7/217

CPC分类号： H02M3/3381

摘要： A switching power supply unit containing a DC power supply; a transformer having a primary winding, a secondary winding and a feedback winding, a main switching element connected in series to the primary winding to be turned on by a voltage generated at the feedback winding, and a voltage dropping circuit for dropping the output voltage obtained form the secondary winding to reduce a fly-back voltage so that the voltage of a control terminal of the main switching element is maintained at a lower value than a threshold voltage of the main switching element.

摘要翻译： 一种包含直流电源的开关电源单元; 具有初级绕组，次级绕组和反馈绕组的变压器，通过在反馈绕组产生的电压而与初级绕组串联连接的主开关元件和用于降低所获得的输出电压的降压电路 形成次级绕组以减小回扫电压，使得主开关元件的控制端子的电压保持在比主开关元件的阈值电压低的值。

公开(公告)号：US6081433A

公开(公告)日：2000-06-27

申请号：US235655

申请日：1999-01-22

申请人： Akio Nishida ,  Koji Nakahira ,  Ryota Tani

发明人： Akio Nishida ,  Koji Nakahira ,  Ryota Tani

IPC分类号： H02M3/28 ,  H02M3/335 ,  H02M3/338

CPC分类号： H02M3/335 ,  H02M3/33523

摘要： A switching power supply apparatus comprises: a transformer having a primary winding, a secondary winding, and a feedback winding; a switching element connected in series with the primary winding; a control circuit provided between a control terminal of the switching element and the feedback winding; and a rectifying circuit connected to the secondary winding. The control element is provided between the control terminal of the switching element and one end of the feedback winding, and a delay circuit is connected to the control terminal of the control element.

摘要翻译： 开关电源装置包括：具有初级绕组，次级绕组和反馈绕组的变压器; 与初级绕组串联连接的开关元件; 控制电路，设置在所述开关元件的控制端子与所述反馈绕组之间; 以及与次级绕组连接的整流电路。 控制元件设置在开关元件的控制端子和反馈绕组的一端之间，并且延迟电路连接到控制元件的控制端子。

公开(公告)号：US20110230041A1

公开(公告)日：2011-09-22

申请号：US13150768

申请日：2011-06-01

申请人： Hiraku CHAKIHARA ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

发明人： Hiraku CHAKIHARA ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

IPC分类号： H01L21/283

CPC分类号： H01L29/6675 ,  H01L21/823885 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/7833 ,  H01L29/78642

摘要： Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.

摘要翻译： 垂直MISFET形成在驱动MISFET和传输MISFET上。 垂直MISFET包括通过层叠下半导体层（漏极），中间半导体层和上半导体层（源极）形成的矩形柱层叠体以及在层叠体的相应侧壁上形成有栅极绝缘膜的栅电极 插入其间。 在每个垂直MISFET中，下半导体层构成漏极，中间半导体层构成衬底（沟道区），上半导体层构成源极。 下半导体层，中间半导体层和上半导体层均由硅膜构成。 下半导体层和上半导体层掺杂有p型并由p型硅膜构成。

公开(公告)号：US07985678B2

公开(公告)日：2011-07-26

申请号：US12896933

申请日：2010-10-04

申请人： Hiraku Chakihara ,  Mitsuhiro Noguchi ,  Masahiro Tadokoro ,  Naonori Wada ,  Akio Nishida

发明人： Hiraku Chakihara ,  Mitsuhiro Noguchi ,  Masahiro Tadokoro ,  Naonori Wada ,  Akio Nishida

IPC分类号： H01L21/44

CPC分类号： H01L27/1104 ,  H01L27/11

摘要： In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light.

摘要翻译： 在形成五个埋入中间导电层的沟槽中，用于连接转移MISFET和驱动MISFET与其上形成的垂直MISFET，其中第二和第三沟槽以及第一，第四和第五沟槽分别通过使用第一和第二 光刻胶膜作为掩模。 由于即使在第一沟槽和第二或第三沟槽之间的最短距离以及第二沟槽和第三沟槽与第四沟槽之间的最短距离小于分辨率极限的情况下，也可以以高精度形成所有沟槽 对于曝光光，布置在一个相同存储单元中的五个沟槽中的每一个之间的距离可以减小到小于曝光光的分辨率极限。

公开(公告)号：US07833905B2

公开(公告)日：2010-11-16

申请号：US12435446

申请日：2009-05-05

申请人： Hiraku Chakihara ,  Mitsuhiro Noguchi ,  Masahiro Tadokoro ,  Naonori Wada ,  Akio Nishida

发明人： Hiraku Chakihara ,  Mitsuhiro Noguchi ,  Masahiro Tadokoro ,  Naonori Wada ,  Akio Nishida

IPC分类号： H01L21/44

CPC分类号： H01L27/1104 ,  H01L27/11

摘要： In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light.

摘要翻译： 在形成五个埋入中间导电层的沟槽中，用于连接转移MISFET和驱动MISFET与其上形成的垂直MISFET，其中第二和第三沟槽以及第一，第四和第五沟槽分别通过使用第一和第二 光刻胶膜作为掩模。 由于即使在第一沟槽和第二或第三沟槽之间的最短距离以及第二沟槽和第三沟槽与第四沟槽之间的最短距离小于分辨率极限的情况下，也可以以高精度形成所有沟槽 对于曝光光，布置在一个相同存储单元中的五个沟槽中的每一个之间的距离可以减小到小于曝光光的分辨率极限。

公开(公告)号：US20090286354A1

公开(公告)日：2009-11-19

申请号：US12508775

申请日：2009-07-24

申请人： KAZUHITO MATSUKAWA ,  Tsuyoshi Koga ,  Akio Nishida ,  Yoshiko Higashide ,  Jun Shibata ,  Hiroshi Tobimatsu

发明人： KAZUHITO MATSUKAWA ,  Tsuyoshi Koga ,  Akio Nishida ,  Yoshiko Higashide ,  Jun Shibata ,  Hiroshi Tobimatsu

IPC分类号： H01L21/98 ,  H01L21/78

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： In a semiconductor chip A wherein an element layer 2 having transistors and the like is formed on the front face, and the back face is joined to an underlying member, such as a package substrate, the thickness T is made 100 μm or less, and thereafter, a gettering layer 3 is formed on the back face of the semiconductor chip A. The gettering layer 3 is formed, for example, by polishing the back face of said semiconductor chip A using a polishing machine. Thereby, the yield of devices can be improved in the step for assembling the package.

摘要翻译： 在半导体芯片A中，其中在正面上形成具有晶体管等的元件层2，并且背面与诸如封装基板的底层部件接合，厚度T为100μm以下， 此后，在半导体芯片A的背面上形成吸气层3.吸气层3例如通过使用研磨机对所述半导体芯片A的背面进行研磨而形成。 因此，在组装包装的步骤中可以提高装置的产量。

公开(公告)号：US20090200870A1

公开(公告)日：2009-08-13

申请号：US10595276

申请日：2005-02-17

申请人： Yoshiyuki Uno ,  Akio Nishida ,  Hiroshi Takemura

发明人： Yoshiyuki Uno ,  Akio Nishida ,  Hiroshi Takemura

IPC分类号： H02J3/00

CPC分类号： H02M3/155 ,  H02M7/17 ,  H02M7/2176 ,  Y10T307/696

摘要： A power supply unit includes a main power-supply circuit and a secondary power-supply circuit which are connected to an alternating current power supply AC. The main power-supply circuit includes a full-wave rectifier and an input current control circuit corresponding to a harmonic current suppression circuit. The input current control circuit includes a resistor as circuit current detection element and a control circuit for controlling a switch element by detecting a current flowing in the resistor. A connection is provided such that a current flowing in a diode as a second rectifying circuit of the secondary power-supply circuit may return to the alternating current power supply through the resistor.

摘要翻译： 电源单元包括连接到交流电源AC的主电源电路和二次电源电路。 主电源电路包括全波整流器和对应于谐波电流抑制电路的输入电流控制电路。 输入电流控制电路包括作为电路电流检测元件的电阻器和用于通过检测在电阻器中流动的电流来控制开关元件的控制电路。 提供连接，使得在二次电源中作为第二电源电路的第二整流电路流动的电流可以通过电阻器返回到交流电源。